公开(公告)号：US11018242B2

公开(公告)日：2021-05-25

申请号：US17011265

申请日：2020-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Li ,  Bi-Fen Wu ,  Jen-Hsiang Lu ,  Chih-Hao Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US11417748B2

公开(公告)日：2022-08-16

申请号：US16735660

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Bi-Fen Wu ,  Chi-On Chui

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

公开(公告)号：US20210134971A1

公开(公告)日：2021-05-06

申请号：US16735660

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Ko ,  Bi-Fen Wu ,  Chi-On Chui

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/8234

Abstract: A semiconductor device including a gate structure disposed on a substrate is provided. The gate structure includes a work function setting layer and a work function tuning layer sequentially disposed on substrate. The work function tuning layer is in contact with an interface surface positioned between the work function setting layer and the work function tuning layer, and a material of the interface surface is different from the work function setting layer.

公开(公告)号：US20210288162A1

公开(公告)日：2021-09-16

申请号：US17328046

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Li ,  Bi-Fen Wu ,  Jen-Hsiang Lu ,  Chih-Hao Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US11810963B2

公开(公告)日：2023-11-07

申请号：US17328046

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Li ,  Bi-Fen Wu ,  Jen-Hsiang Lu ,  Chih-Hao Chang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L29/66545 ,  H01L21/2815 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823468

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.