公开(公告)号：US20190006245A1

公开(公告)日：2019-01-03

申请号：US16102140

申请日：2018-08-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L21/8234 ,  H01L29/423 ,  H01L27/088 ,  H01L21/28 ,  H01L21/762

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.

公开(公告)号：US20200373317A1

公开(公告)日：2020-11-26

申请号：US16989778

申请日：2020-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chin LIU ,  Wei Cheng WU ,  Yi Hsien LU ,  Yu-Hsiung WANG ,  Juo-Li YANG

IPC: H01L27/11546 ,  G11C16/04 ,  G11C16/12 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/11548 ,  H01L29/788 ,  H01L27/088

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US20200266196A1

公开(公告)日：2020-08-20

申请号：US16866506

申请日：2020-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L27/11575 ,  H01L27/11526 ,  H01L27/11546 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/761 ,  H01L21/266

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US20200027889A1

公开(公告)日：2020-01-23

申请号：US16588090

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chin LIU ,  Wei Cheng WU ,  Yi Hsien LU ,  Yu-Hsiung WANG ,  Juo-Li YANG

IPC: H01L27/11546 ,  H01L27/088 ,  H01L29/788 ,  H01L21/28 ,  H01L27/105 ,  H01L27/11 ,  G11C16/12 ,  G11C16/04 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/11548

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US20190088558A1

公开(公告)日：2019-03-21

申请号：US16195008

申请日：2018-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L21/8238 ,  H01L21/266 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/762 ,  H01L21/761

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US20190006380A1

公开(公告)日：2019-01-03

申请号：US15725000

申请日：2017-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Chin LIU ,  Wei Cheng WU ,  Yi Hsien LU ,  Yu-Hsiung WANG ,  Juo-Li YANG

IPC: H01L27/11546 ,  H01L27/088 ,  H01L29/423 ,  H01L29/788 ,  G11C16/04 ,  H01L27/105 ,  H01L27/11 ,  G11C16/12 ,  H01L21/28

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US20180090392A1

公开(公告)日：2018-03-29

申请号：US15782588

申请日：2017-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/762 ,  H01L21/761

CPC classification number: H01L21/823892 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0928

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US20180005897A1

公开(公告)日：2018-01-04

申请号：US15216569

申请日：2016-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/762 ,  H01L29/423

CPC classification number: H01L21/823462 ,  H01L21/28158 ,  H01L21/76224 ,  H01L29/42364

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.