公开(公告)号：US20180151581A1

公开(公告)日：2018-05-31

申请号：US15428823

申请日：2017-02-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng WU ,  Li-Feng TENG

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11536 ,  H01L27/11541 ,  H01L27/11543 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66545

Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.

公开(公告)号：US20210066327A1

公开(公告)日：2021-03-04

申请号：US17094758

申请日：2020-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wei Cheng WU

IPC: H01L27/11541 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/285 ,  H01L29/788 ,  H01L21/8239 ,  H01L21/306 ,  H01L29/66

Abstract: A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

公开(公告)号：US20200075613A1

公开(公告)日：2020-03-05

申请号：US16545713

申请日：2019-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wei Cheng WU

IPC: H01L27/11521 ,  H01L27/11526

Abstract: A method is provided for the manufacture of an integrated semiconductor device that includes an embedded flash memory array formed in a recessed region of a semiconductor substrate, the method includes, prior to formation of floating and control gate stacks of the memory array, depositing a protective layer over layers of gate material, and depositing a self-leveling sacrificial layer over the protective layer to produce a substantially planar upper surface. The sacrificial layer is then etched to a depth that removes the sacrificial layer and leaves a substantially planar face on the protective layer. A photo mask is then deposited on the protective layer and the gate stacks are etched from the layers of gate material.

公开(公告)号：US20180277553A1

公开(公告)日：2018-09-27

申请号：US15987089

申请日：2018-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng WU ,  Jui-Tsung LIEN

IPC: H01L27/11524 ,  H01L27/11548 ,  H01L21/02 ,  H01L29/06 ,  H01L21/308 ,  H01L29/788 ,  H01L27/11534 ,  H01L29/66

CPC classification number: H01L27/11524 ,  H01L21/02271 ,  H01L21/3081 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11548 ,  H01L29/0649 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area. The mask layer in the memory cell area is patterned by using the resist mask as an etching mask. The substrate is etched in the memory cell area. After etching the substrate, a memory cell structure in the memory cell area and a gate structure for the logic circuit are formed. A dielectric layer is formed to cover the memory cell structure and the gate structure. A planarization operation is performed on the dielectric layer. An upper portion of the memory cell structure is planarized during the planarization operation.

公开(公告)号：US20230354600A1

公开(公告)日：2023-11-02

申请号：US18346056

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wei Cheng WU

IPC: H10B41/47 ,  H01L29/423 ,  H01L21/285 ,  H01L29/788 ,  H01L21/306 ,  H01L29/66 ,  H10B41/30 ,  H10B99/00

CPC classification number: H10B41/47 ,  H01L29/42328 ,  H01L21/28518 ,  H01L29/788 ,  H01L21/30625 ,  H01L29/66825 ,  H10B41/30 ,  H10B99/00

Abstract: A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

公开(公告)号：US20210343734A1

公开(公告)日：2021-11-04

申请号：US17374591

申请日：2021-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wei Cheng WU

IPC: H01L27/11521 ,  H01L27/11526

Abstract: A device has a semiconductor substrate including a recessed region. The recessed region has a center portion and a periphery portion. An isolation region abuts the periphery portion. A plurality of gate stacks are in the recessed region. A protective layer overlying the plurality of gate stacks and the isolation region has a substantially planar upper surface across the recessed region and the isolation region.

公开(公告)号：US20210343733A1

公开(公告)日：2021-11-04

申请号：US17374573

申请日：2021-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wei Cheng WU

IPC: H01L27/11521 ,  H01L27/11526

Abstract: A method includes planarizing a protective layer over gate materials overlying a recessed region in a substrate. The planarizing includes forming a first planarized surface by planarizing a sacrificial layer over the protective layer, and forming a second planarized surface of the protective layer by etching the first planarized surface of the sacrificial layer at an even rate across the recessed region. An etch mask layer is formed over the second planarized surface, and control gate stacks are formed in the recessed region by etching the gate materials.

公开(公告)号：US20200373317A1

公开(公告)日：2020-11-26

申请号：US16989778

申请日：2020-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chin LIU ,  Wei Cheng WU ,  Yi Hsien LU ,  Yu-Hsiung WANG ,  Juo-Li YANG

IPC: H01L27/11546 ,  G11C16/04 ,  G11C16/12 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/11548 ,  H01L29/788 ,  H01L27/088

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US20200027889A1

公开(公告)日：2020-01-23

申请号：US16588090

申请日：2019-09-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Chin LIU ,  Wei Cheng WU ,  Yi Hsien LU ,  Yu-Hsiung WANG ,  Juo-Li YANG

IPC: H01L27/11546 ,  H01L27/088 ,  H01L29/788 ,  H01L21/28 ,  H01L27/105 ,  H01L27/11 ,  G11C16/12 ,  G11C16/04 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/11548

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US20180083019A1

公开(公告)日：2018-03-22

申请号：US15267954

申请日：2016-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei Cheng WU ,  Jui-Tsung LIEN

IPC: H01L27/115 ,  H01L29/06 ,  H01L21/308 ,  H01L29/66 ,  H01L29/788 ,  H01L21/02

CPC classification number: H01L27/11524 ,  H01L21/02271 ,  H01L21/28273 ,  H01L21/3081 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11548 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area. The mask layer in the memory cell area is patterned by using the resist mask as an etching mask. The substrate is etched in the memory cell area. After etching the substrate, a memory cell structure in the memory cell area and a gate structure for the logic circuit are formed. A dielectric layer is formed to cover the memory cell structure and the gate structure. A planarization operation is performed on the dielectric layer. An upper portion of the memory cell structure is planarized during the planarization operation.