公开(公告)号：US20240170551A1

公开(公告)日：2024-05-23

申请号：US18430522

申请日：2024-02-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Wei-Cheng WU ,  Te-Hsin CHIU

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L29/42368 ,  H01L21/02244 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, a dielectric structure, and a spacer. The control gate and the select gate are over a channel region of the semiconductor substrate and separated from each other. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part. The select gate is between the spacer and the control gate, and the select gate is separated from the spacer by the second part of the dielectric structure.

公开(公告)号：US20220130975A1

公开(公告)日：2022-04-28

申请号：US17081012

申请日：2020-10-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chia-En HUANG

IPC: H01L29/49 ,  H01L27/11 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/3215 ,  H01L21/762 ,  H01L29/66

Abstract: An integrated chip includes a substrate, an isolation structure and a poly gate structure. The isolation structure includes dielectric materials within the substrate and having sidewalls defining an active region. The active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction. The source region has a first width along a second direction perpendicular to the first direction, the drain region has a second width along the second direction, and the channel region has a third width along the second direction and larger than the first and second widths. The poly gate structure extends over the channel region. The poly gate structure includes a first doped region having a first type of dopants and a second doped region having a second type of dopants. The second type is different from the first type.

公开(公告)号：US20210066327A1

公开(公告)日：2021-03-04

申请号：US17094758

申请日：2020-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wei Cheng WU

IPC: H01L27/11541 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/285 ,  H01L29/788 ,  H01L21/8239 ,  H01L21/306 ,  H01L29/66

Abstract: A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

公开(公告)号：US20200075613A1

公开(公告)日：2020-03-05

申请号：US16545713

申请日：2019-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Wei Cheng WU

IPC: H01L27/11521 ,  H01L27/11526

Abstract: A method is provided for the manufacture of an integrated semiconductor device that includes an embedded flash memory array formed in a recessed region of a semiconductor substrate, the method includes, prior to formation of floating and control gate stacks of the memory array, depositing a protective layer over layers of gate material, and depositing a self-leveling sacrificial layer over the protective layer to produce a substantially planar upper surface. The sacrificial layer is then etched to a depth that removes the sacrificial layer and leaves a substantially planar face on the protective layer. A photo mask is then deposited on the protective layer and the gate stacks are etched from the layers of gate material.

公开(公告)号：US20160308071A1

公开(公告)日：2016-10-20

申请号：US14690209

申请日：2015-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chien-Chih CHOU ,  Chih-Wen HSIUNG ,  Kong-Beng THEI

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/47 ,  H01L21/02 ,  H01L21/762 ,  H01L21/225 ,  H01L29/66 ,  H01L21/324

CPC classification number: H01L29/872 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/66143

Abstract: A method of manufacturing a Schottky barrier diode is provided, which includes: providing a semiconductor substrate including a first well region of a first conductivity type in the semiconductor substrate; forming a surface-doped layer having a dopant of a second conductivity type opposite to the first conductivity type in the first well region; forming a dielectric layer in contact with the surface-doped layer; performing a thermal treatment on the surface-doped layer to move the dopant of the surface-doped layer in the dielectric layer; removing the dielectric layer to expose the first well region; and forming a silicide layer in contact with the exposed first well region. A Schottky barrier diode is also provided.

Abstract translation: 提供一种制造肖特基势垒二极管的方法，其包括：在半导体衬底中提供包括第一导电类型的第一阱区的半导体衬底; 在所述第一阱区中形成具有与所述第一导电类型相反的第二导电类型的掺杂剂的表面掺杂层; 形成与表面掺杂层接触的介电层; 对所述表面掺杂层进行热处理，以移动所述介电层中的所述表面掺杂层的掺杂剂; 去除介电层以露出第一阱区; 以及形成与暴露的第一阱区域接触的硅化物层。 还提供肖特基势垒二极管。

公开(公告)号：US20210184012A1

公开(公告)日：2021-06-17

申请号：US17185915

申请日：2021-02-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Wei-Cheng WU ,  Te-Hsin CHIU

IPC: H01L29/423 ,  H01L29/792 ,  H01L21/02 ,  H01L29/66 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/1157

Abstract: A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, and a dielectric structure. The semiconductor substrate has a drain region, a source region, and a channel region between the drain region and the source region. The control gate is over the channel region of the semiconductor substrate. The select gate is over the channel region of the semiconductor substrate and separated from the control gate. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part.

公开(公告)号：US20210013220A1

公开(公告)日：2021-01-14

申请号：US16506823

申请日：2019-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Wen-Tuo HUANG ,  Yong-Shiuan TSAIR

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/788 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and a first gate stack. An isolation feature is formed in the semiconductor substrate, and a cell region and a peripheral region adjacent to the cell region are defined in the semiconductor substrate. The first gate stack is disposed on the peripheral region of the semiconductor substrate. The first gate stack includes a first dielectric layer and a gate electrode layer disposed on the first dielectric layer and covering a top surface of the first dielectric layer. The first dielectric layer is disposed on the semiconductor substrate and has a concave profile.

公开(公告)号：US20200168701A1

公开(公告)日：2020-05-28

申请号：US16572357

申请日：2019-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren Hsieh

IPC: H01L29/06 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529

Abstract: A method includes forming a shallow trench isolation (STI) region in a semiconductor substrate, the STI region bordering an active region in the semiconductor substrate; forming a plurality of gate structures over the semiconductor substrate; and forming a plurality of conductive contacts between the gate structures and in contact with the STI region, wherein a portion of the active region is between the conductive contacts.

公开(公告)号：US20200027890A1

公开(公告)日：2020-01-23

申请号：US16585809

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chin Wen CHAN

IPC: H01L27/11548 ,  H01L27/11534 ,  H01L27/11526

Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.

公开(公告)号：US20180182772A1

公开(公告)日：2018-06-28

申请号：US15698469

申请日：2017-09-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chin Wen CHAN

IPC: H01L27/11548 ,  H01L27/11526 ,  H01L27/11519

Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.