公开(公告)号：US20210217892A1

公开(公告)日：2021-07-15

申请号：US16743926

申请日：2020-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Cheng WU ,  Chih-Ren HSIEH

IPC: H01L29/788 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66

Abstract: A memory device includes a semiconductor fin, a floating gate, a control gate, a source region, an erase gate, and a select gate. The floating gate is above and conformal to the semiconductor fin. The control gate is above the floating gate. The source region is in the semiconductor fin. The erase gate is above the source region and adjacent the control gate. The select gate is above the semiconductor fin. The control gate is between the erase gate and the select gate.

公开(公告)号：US20210226027A1

公开(公告)日：2021-07-22

申请号：US16745219

申请日：2020-01-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yong-Sheng HUANG ,  Ming-Chyi LIU ,  Chih-Ren HSIEH

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11524

Abstract: A semiconductor device includes an erase gate electrode, an erase gate dielectric, first and second floating gate electrodes, first and second control gate electrodes, a first select gate electrode, a second select gate electrode, a common source strap, and a silicide pad. The erase gate electrode is over a first portion of a substrate. The common source strap is over a second portion of the substrate, in which the common source strap and the erase gate electrode are arranged along a second direction perpendicular to the first direction. The silicide pad is under the common source strap and in the second portion of the substrate, wherein a top surface of the silicide pad is flatter than a bottom surface of the erase gate dielectric.

公开(公告)号：US20200266196A1

公开(公告)日：2020-08-20

申请号：US16866506

申请日：2020-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L27/11575 ,  H01L27/11526 ,  H01L27/11546 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/761 ,  H01L21/266

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US20210249429A1

公开(公告)日：2021-08-12

申请号：US16787952

申请日：2020-02-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Chyi LIU ,  Chih-Ren HSIEH ,  Sheng-Chieh CHEN

IPC: H01L27/11521 ,  H01L21/28 ,  H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3105 ,  H01L29/788 ,  H01L29/423

Abstract: A semiconductor device includes a substrate, an isolation feature, a floating gate, and a control gate. The substrate has a protruding portion. The isolation feature surrounds the protruding portion of the substrate. The floating gate is over the protruding portion of the substrate, in which a sidewall of the floating gate is aligned with a sidewall of the protruding portion of the substrate. The control gate is over the floating gate.

公开(公告)号：US20200027890A1

公开(公告)日：2020-01-23

申请号：US16585809

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chin Wen CHAN

IPC: H01L27/11548 ,  H01L27/11534 ,  H01L27/11526

Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.

公开(公告)号：US20180182772A1

公开(公告)日：2018-06-28

申请号：US15698469

申请日：2017-09-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chin Wen CHAN

IPC: H01L27/11548 ,  H01L27/11526 ,  H01L27/11519

Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.

公开(公告)号：US20190088558A1

公开(公告)日：2019-03-21

申请号：US16195008

申请日：2018-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L21/8238 ,  H01L21/266 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/762 ,  H01L21/761

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US20180315765A1

公开(公告)日：2018-11-01

申请号：US15904678

申请日：2018-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chin-Wen CHAN ,  Chih-Ren HSIEH

IPC: H01L27/11521 ,  H01L27/11519 ,  H01L21/762 ,  H01L29/06

Abstract: An integrated circuit includes a substrate, a first isolation feature, and a plurality of memory cells. The substrate has a cell region, a peripheral region, and a transition region between the cell region and the peripheral region. A top surface of the cell region is lower than a top surface of the peripheral region, and the substrate includes at least one protrusion portion in the transition region. The first isolation feature is in the transition region and covers the protrusion portion of the substrate. The memory cells are over the cell region of the substrate.

公开(公告)号：US20180090392A1

公开(公告)日：2018-03-29

申请号：US15782588

申请日：2017-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/762 ,  H01L21/761

CPC classification number: H01L21/823892 ,  H01L21/266 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0928

Abstract: A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

公开(公告)号：US20180005897A1

公开(公告)日：2018-01-04

申请号：US15216569

申请日：2016-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han LIN ,  Chih-Ren HSIEH ,  Chen-Chin LIU

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/762 ,  H01L29/423

CPC classification number: H01L21/823462 ,  H01L21/28158 ,  H01L21/76224 ,  H01L29/42364

Abstract: In a method of manufacturing a semiconductor device, an isolation region is formed in a substrate, such that the isolation region surrounds an active region of the substrate in plan view. A first dielectric layer is formed over the active region. A mask layer is formed on a gate region of the first dielectric layer. The gate region includes a region where a gate electrode is to be formed. The mask layer covers the gate region, but does not entirely cover the first dielectric layer. The first dielectric layer not covered by the mask layer is removed such that a source-drain region of the active region is exposed. After that, the mask layer is removed. A second dielectric layer is formed so that a gate dielectric layer is formed. The gate electrode is formed over the gate dielectric layer.