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    Local Gate Height Tuning by Cmp And Dummy Gate Design
    1.
    发明申请
    Local Gate Height Tuning by Cmp And Dummy Gate Design 有权

    公开(公告)号：US20210202320A1

    公开(公告)日：2021-07-01

    申请号：US17125299

    申请日：2020-12-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Chang Wen ,  Chang-Yun Chang ,  Keng-Yao Chen ,  Chen-Yu Tai ,  Yi-Ting Fu

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/321

    Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.

    INSULATING STRUCTURES IN SEMICONDUCTOR DEVICE
    4.
    发明公开
    INSULATING STRUCTURES IN SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230395654A1

    公开(公告)日：2023-12-07

    申请号：US17832495

    申请日：2022-06-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tzu-Ging LIN ,  Chen-Yu Tai

    IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/762 ,  H01L29/66

    CPC classification number: H01L29/0649 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/76224 ,  H01L29/66545 ,  H01L29/66742

    Abstract: The present disclosure describes a structure that provides insulation in a semiconductor device and a method for forming the structure. The structure includes a first isolation structure including a first isolation layer disposed on a substrate, a second isolation layer disposed on the first isolation layer, and a first high-k dielectric layer having a first height and disposed on the second isolation layer. The structure further includes a second isolation structure including a third isolation layer disposed on the substrate, a fourth isolation layer disposed on the third isolation layer, and a second high-k dielectric layer having a second height and disposed on the fourth isolation layer, where the second height is less than the first height. The structure further includes a gate structure disposed on the first isolation structure, and an insulating structure disposed adjacent to the gate structure and on the second isolation structure.

    Local Gate Height Tuning by Cmp And Dummy Gate Design
    6.
    发明申请
    Local Gate Height Tuning by Cmp And Dummy Gate Design 有权

    公开(公告)号：US20220384262A1

    公开(公告)日：2022-12-01

    申请号：US17884324

    申请日：2022-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Chang Wen ,  Chang-Yun Chang ,  Keng-Yao Chen ,  Chen-Yu Tai ,  Yi-Ting Fu

    IPC: H01L21/8234 ,  H01L21/321 ,  H01L29/66 ,  H01L21/306

    Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height different from a second height of the second metal gate stack.

    Local gate height tuning by CMP and dummy gate design
    7.
    发明授权
    Local gate height tuning by CMP and dummy gate design 有权

    公开(公告)号：US11508623B2

    公开(公告)日：2022-11-22

    申请号：US17125299

    申请日：2020-12-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Chang Wen ,  Chang-Yun Chang ,  Keng-Yao Chen ,  Chen-Yu Tai ,  Yi-Ting Fu

    IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/66 ,  H01L21/306

    Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.

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