公开(公告)号：US20230386927A1

公开(公告)日：2023-11-30

申请号：US18365405

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chang Wen ,  Chang-Yun Chang ,  Keng-Yao Chen ,  Chen-Yu Tai ,  Yi-Ting Fu

IPC: H01L21/8234 ,  H01L21/321 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/82345 ,  H01L21/3212 ,  H01L29/66545 ,  H01L21/823431 ,  H01L21/30625 ,  H01L21/823456

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, and performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles. The first and second metal gate stacks are different in composition. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.

公开(公告)号：US20220285529A1

公开(公告)日：2022-09-08

申请号：US17664479

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Tai-Chun Huang ,  Ming-Chang Wen ,  Shu-Yuan Ku ,  Fu-Kai Yang ,  Tze-Liang Lee ,  Yung-Cheng Lu ,  Yi-Ting Fu

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/762 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/311

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

公开(公告)号：US20210202320A1

公开(公告)日：2021-07-01

申请号：US17125299

申请日：2020-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chang Wen ,  Chang-Yun Chang ,  Keng-Yao Chen ,  Chen-Yu Tai ,  Yi-Ting Fu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/321

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.

公开(公告)号：US12243782B2

公开(公告)日：2025-03-04

申请号：US18365405

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chang Wen ,  Chang-Yun Chang ,  Keng-Yao Chen ,  Chen-Yu Tai ,  Yi-Ting Fu

IPC: H01L21/00 ,  H01L21/306 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/66

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, and performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles. The first and second metal gate stacks are different in composition. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.

公开(公告)号：US20240347623A1

公开(公告)日：2024-10-17

申请号：US18753240

申请日：2024-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Tai-Chun Huang ,  Ming-Chang Wen ,  Shu-Yuan Ku ,  Fu-Kai Yang ,  Tze-Liang Lee ,  Yung-Cheng Lu ,  Yi-Ting Fu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

公开(公告)号：US12051735B2

公开(公告)日：2024-07-30

申请号：US17664479

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Gang Chen ,  Tai-Chun Huang ,  Ming-Chang Wen ,  Shu-Yuan Ku ,  Fu-Kai Yang ,  Tze-Liang Lee ,  Yung-Cheng Lu ,  Yi-Ting Fu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer.

公开(公告)号：US11817354B2

公开(公告)日：2023-11-14

申请号：US17884324

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chang Wen ,  Chang-Yun Chang ,  Keng-Yao Chen ,  Chen-Yu Tai ,  Yi-Ting Fu

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/82345 ,  H01L21/30625 ,  H01L21/3212 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/66545

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height different from a second height of the second metal gate stack.

公开(公告)号：US20220384262A1

公开(公告)日：2022-12-01

申请号：US17884324

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chang Wen ,  Chang-Yun Chang ,  Keng-Yao Chen ,  Chen-Yu Tai ,  Yi-Ting Fu

IPC: H01L21/8234 ,  H01L21/321 ,  H01L29/66 ,  H01L21/306

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height different from a second height of the second metal gate stack.

公开(公告)号：US11508623B2

公开(公告)日：2022-11-22

申请号：US17125299

申请日：2020-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Chang Wen ,  Chang-Yun Chang ,  Keng-Yao Chen ,  Chen-Yu Tai ,  Yi-Ting Fu

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/66 ,  H01L21/306

Abstract: The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.