公开(公告)号：US20160211010A1

公开(公告)日：2016-07-21

申请号：US15071686

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-I YANG ,  Yi-Tzu Chen ,  Cheng-Jen Chang ,  Geng-Cing Lin ,  Yu-Hao Hu

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C11/412 ,  G11C11/418 ,  H01L27/11551

Abstract: A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.

Abstract translation: 半导体存储器包括至少包括第一存储单元的第一层，至少包括第二存储单元的第二层和由第一存储单元和第二存储单元共享的字线。 第一和第二存储器单元可以在字线的上方或下方并且耦合到不同的位线。

公开(公告)号：US09299391B2

公开(公告)日：2016-03-29

申请号：US14159464

申请日：2014-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-I Yang ,  Yi-Tzu Chen ,  Cheng-Jen Chang ,  Geng-Cing Lin ,  Yu-Hao Hu

IPC: G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  H01L27/115

CPC classification number: G11C11/417 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C11/412 ,  G11C11/418 ,  H01L27/11551

Abstract: A three dimensional (3D) circuit includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be adjacent memory cells or bit cells coupled to different bit lines.

Abstract translation: 三维（3D）电路包括包括至少第一存储器单元的第一层，包括至少第二存储单元的第二层和由第一存储单元和第二存储单元共享的字线。 第一和第二存储器单元可以是与不同位线耦合的相邻存储器单元或位单元。

公开(公告)号：US09711209B2

公开(公告)日：2017-07-18

申请号：US15071686

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-I Yang ,  Yi-Tzu Chen ,  Cheng-Jen Chang ,  Geng-Cing Lin ,  Yu-Hao Hu

IPC: G11C5/02 ,  G11C11/417 ,  G11C5/06 ,  G11C8/14 ,  H01L27/11551 ,  G11C11/412 ,  G11C11/418

CPC classification number: G11C11/417 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C11/412 ,  G11C11/418 ,  H01L27/11551

Abstract: A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.