公开(公告)号：US20160211010A1

公开(公告)日：2016-07-21

申请号：US15071686

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-I YANG ,  Yi-Tzu Chen ,  Cheng-Jen Chang ,  Geng-Cing Lin ,  Yu-Hao Hu

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C11/412 ,  G11C11/418 ,  H01L27/11551

Abstract: A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.

Abstract translation: 半导体存储器包括至少包括第一存储单元的第一层，至少包括第二存储单元的第二层和由第一存储单元和第二存储单元共享的字线。 第一和第二存储器单元可以在字线的上方或下方并且耦合到不同的位线。

公开(公告)号：US09007851B2

公开(公告)日：2015-04-14

申请号：US13753609

申请日：2013-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Yuan Chen ,  Hau-Tai Shieh ,  Yi-Tzu Chen ,  Hong-Chen Cheng

IPC: G11C7/10 ,  H03F3/16 ,  G11C7/06 ,  G11C11/419

CPC classification number: H03F3/16 ,  G11C7/065 ,  G11C7/1048 ,  G11C11/419 ,  G11C2207/002

Abstract: Some embodiments relate to a sense amplifier output buffer configured to buffer an output of a sense amplifier. The sense amplifier output buffer includes a first pull-up element having a source coupled to a first DC supply terminal and having a drain coupled to an output terminal of the sense amplifier output buffer. A first pull-down element is in series with the first pull-up element and has a source coupled to a second DC supply terminal and has a drain coupled to the output terminal. A miller capacitance decoupling circuit is coupled between the drain of the first pull-up element and the drain of the first pull-down element. The miller capacitance decoupling circuit is configured to decouple miller capacitance associated with the drains of the pull-up and pull-down elements from the output terminal. Other embodiments are also disclosed.

Abstract translation: 一些实施例涉及被配置为缓冲读出放大器的输出的读出放大器输出缓冲器。 读出放大器输出缓冲器包括第一上拉元件，其具有耦合到第一DC电源端子的源极，并且具有耦合到读出放大器输出缓冲器的输出端子的漏极。 第一下拉元件与第一上拉元件串联并且具有耦合到第二DC电源端子的源极，并且具有耦合到输出端子的漏极。 铣刀电容去耦电路耦合在第一上拉元件的漏极和第一下拉元件的漏极之间。 铣刀电容去耦电路被配置为将与上拉和下拉元件的漏极相关联的铣刀电容从输出端子去耦。 还公开了其他实施例。

公开(公告)号：US20140211570A1

公开(公告)日：2014-07-31

申请号：US13753609

申请日：2013-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Yuan Chen ,  Hau-Tai Shieh ,  Yi-Tzu Chen ,  Hong-Chen Cheng

IPC: G11C7/06 ,  H03F3/16 ,  G11C7/10

CPC classification number: H03F3/16 ,  G11C7/065 ,  G11C7/1048 ,  G11C11/419 ,  G11C2207/002

Abstract: Some embodiments relate to a sense amplifier output buffer configured to buffer an output of a sense amplifier. The sense amplifier output buffer includes a first pull-up element having a source coupled to a first DC supply terminal and having a drain coupled to an output terminal of the sense amplifier output buffer. A first pull-down element is in series with the first pull-up element and has a source coupled to a second DC supply terminal and has a drain coupled to the output terminal. A miller capacitance decoupling circuit is coupled between the drain of the first pull-up element and the drain of the first pull-down element. The miller capacitance decoupling circuit is configured to decouple miller capacitance associated with the drains of the pull-up and pull-down elements from the output terminal. Other embodiments are also disclosed.

Abstract translation: 一些实施例涉及被配置为缓冲读出放大器的输出的读出放大器输出缓冲器。 读出放大器输出缓冲器包括第一上拉元件，其具有耦合到第一DC电源端子的源极，并且具有耦合到读出放大器输出缓冲器的输出端子的漏极。 第一下拉元件与第一上拉元件串联并且具有耦合到第二DC电源端子的源极，并且具有耦合到输出端子的漏极。 铣刀电容去耦电路耦合在第一上拉元件的漏极和第一下拉元件的漏极之间。 铣刀电容去耦电路被配置为将与上拉和下拉元件的漏极相关联的铣刀电容从输出端子去耦。 还公开了其他实施例。

公开(公告)号：US09711209B2

公开(公告)日：2017-07-18

申请号：US15071686

申请日：2016-03-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-I Yang ,  Yi-Tzu Chen ,  Cheng-Jen Chang ,  Geng-Cing Lin ,  Yu-Hao Hu

IPC: G11C5/02 ,  G11C11/417 ,  G11C5/06 ,  G11C8/14 ,  H01L27/11551 ,  G11C11/412 ,  G11C11/418

CPC classification number: G11C11/417 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C11/412 ,  G11C11/418 ,  H01L27/11551

Abstract: A semiconductor memory includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be above or below the wordline and be coupled to different bit lines.

公开(公告)号：US09299391B2

公开(公告)日：2016-03-29

申请号：US14159464

申请日：2014-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-I Yang ,  Yi-Tzu Chen ,  Cheng-Jen Chang ,  Geng-Cing Lin ,  Yu-Hao Hu

IPC: G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  H01L27/115

CPC classification number: G11C11/417 ,  G11C5/025 ,  G11C5/063 ,  G11C8/14 ,  G11C11/412 ,  G11C11/418 ,  H01L27/11551

Abstract: A three dimensional (3D) circuit includes a first layer including at least a first memory cell, a second layer including at least a second memory cell, and a wordline shared by the first memory cell and the second memory cell. The first and second memory cells can be adjacent memory cells or bit cells coupled to different bit lines.

Abstract translation: 三维（3D）电路包括包括至少第一存储器单元的第一层，包括至少第二存储单元的第二层和由第一存储单元和第二存储单元共享的字线。 第一和第二存储器单元可以是与不同位线耦合的相邻存储器单元或位单元。