公开(公告)号：US09721805B1

公开(公告)日：2017-08-01

申请号：US15223933

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hui Lee ,  Chen-Wei Pan ,  Yi-Wei Chiu ,  Tzu-Chan Weng

IPC: H01L21/76 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/265 ,  H01L29/06 ,  H01L21/84

CPC classification number: H01L21/311 ,  H01L21/02129 ,  H01L21/02321 ,  H01L21/02362 ,  H01L21/02579 ,  H01L21/265 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/7851

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming first and second fin structures over a semiconductor substrate. Each of the first and second fin structures has an upper portion and a lower portion. The method also includes forming a phosphosilicate glass (PSG) layer surrounding the upper and lower portions of the first fin structure. The method further includes doping the PSG layer to form a doped PSG layer. In addition, the method includes forming a borosilicate glass (BSG) layer surrounding the upper and lower portions of the second fin structure. The BSG layer extends over the doped PSG layer. The method also includes forming an isolation layer over the BSG layer. The method further includes partially etching the isolation layer, the BSG layer and the doped PSG layer to expose the upper portions of the first and second fin structures.