公开(公告)号：US20160336412A1

公开(公告)日：2016-11-17

申请号：US14842680

申请日：2015-09-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Cheng HUNG ,  Kei-Wei CHEN ,  Yu-Sheng WANG ,  Ming-Ching CHUNG ,  Chia-Yang WU

IPC: H01L29/417 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41725 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor structure includes a semiconductor substrate, at least one dielectric layer, a dielectric spacer liner (DSL) layer, and at least one conductor. The dielectric layer is present on the semiconductor substrate. The dielectric layer has at least one contact hole exposing at least a portion of the semiconductor substrate. The semiconductor substrate has at least one recess communicating with the contact hole. The recess has a bottom surface and at least one sidewall. The DSL layer is present on at least the sidewall of the recess. The conductor is present at least partially in the contact hole and is electrically connected to the semiconductor substrate.

Abstract translation: 半导体结构包括半导体衬底，至少一个电介质层，介电间隔衬垫（DSL）层和至少一个导体。 电介质层存在于半导体衬底上。 电介质层具有暴露半导体衬底的至少一部分的至少一个接触孔。 半导体衬底具有与接触孔连通的至少一个凹部。 凹部具有底表面和至少一个侧壁。 DSL层至少存在于凹槽的侧壁上。 导体至少部分地存在于接触孔中，并与半导体衬底电连接。

公开(公告)号：US20230268402A1

公开(公告)日：2023-08-24

申请号：US18309506

申请日：2023-04-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Cheng HUNG ,  Kei-Wei CHEN ,  Yu-Sheng WANG ,  Ming-Ching CHUNG ,  Chia-Yang WU

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/285 ,  H01L23/485

CPC classification number: H01L29/41725 ,  H01L29/7848 ,  H01L21/76831 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/0847 ,  H01L29/165 ,  H01L21/28518 ,  H01L23/485 ,  H01L21/76805 ,  H01L29/4966

Abstract: A semiconductor device includes a source/drain region, a silicide region, a source/drain contact, and a silicon-containing dielectric liner. The source/drain region is in a substrate. The silicide region is embedded in the source/drain region. The source/drain contact is over the silicide region. The silicon-containing dielectric liner surrounds the source/drain contact. The source/drain region is in contact with an outer sidewall of the silicon-containing dielectric liner but separated from a bottom surface of the silicon-containing dielectric liner by the silicide region.

公开(公告)号：US20180233565A1

公开(公告)日：2018-08-16

申请号：US15954458

申请日：2018-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Cheng HUNG ,  Kei-Wei CHEN ,  Yu-Sheng WANG ,  Ming-Ching CHUNG ,  Chia-Yang WU

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/165 ,  H01L21/285 ,  H01L23/485 ,  H01L29/49

Abstract: A device includes an epitaxy structure having a recess therein, a dielectric layer over the epitaxy structure, the dielectric layer having a contact hole communicating with the recess, a dielectric spacer liner (DSL) layer on a sidewall of the recess, a barrier layer on the DSL layer, and a conductor. The DSL layer has an opening. The DSL layer extends further into the epitaxy structure than the barrier layer. The conductor is disposed in the contact hole and electrically connected to the epitaxy feature through the opening of the DSL layer.

公开(公告)号：US20200343349A1

公开(公告)日：2020-10-29

申请号：US16926671

申请日：2020-07-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Cheng HUNG ,  Kei-Wei CHEN ,  Yu-Sheng WANG ,  Ming-Ching CHUNG ,  Chia-Yang WU

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/285 ,  H01L23/485

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a first source/drain region, a second source/drain region, first source/drain contact and a first dielectric spacer liner. The gate structure is over the semiconductor substrate. The first source/drain region and the second source/drain region are in the semiconductor substrate and respectively on opposite sides of the gate structure. The first source/drain contact is over the first source/drain region. The first dielectric spacer liner lines a sidewall of the first source/drain contact and extends into the first source/drain region.

公开(公告)号：US20190148522A1

公开(公告)日：2019-05-16

申请号：US16174921

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang WU ,  Shiu-Ko JANGJIAN ,  Ting-Chun WANG ,  Yung-Si YU

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L21/285 ,  H01L29/49 ,  H01L21/762

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric structure over a transistor. The method includes forming a first recess in the dielectric structure. The method includes forming a first barrier layer over a first inner wall of the first recess. The first barrier layer has a first opening over a first portion of the dielectric structure, and the first barrier layer close to a first bottom surface of the first recess is thicker than the first barrier layer close to a top surface of the dielectric structure. The method includes removing the first portion through the first opening to form a second recess in the dielectric structure. The method includes forming a second barrier layer over a second inner wall of the second recess. The method includes forming a contact layer in the first opening and the second opening.

公开(公告)号：US20200251577A1

公开(公告)日：2020-08-06

申请号：US16852973

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang WU ,  Shiu-Ko JANGJIAN ,  Ting-Chun WANG ,  Yung-Si YU

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L21/762 ,  H01L21/285 ,  H01L29/49

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor over a substrate. The semiconductor device structure includes a dielectric structure over the substrate and covering the transistor. The semiconductor device structure includes a contact structure passing through the dielectric structure and electrically connected to the transistor. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, a first lower portion of the first barrier layer is in direct contact with the dielectric structure, and a thickness of the first lower portion increases toward the substrate.

公开(公告)号：US20190067436A1

公开(公告)日：2019-02-28

申请号：US15690693

申请日：2017-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang WU ,  Shiu-Ko JANG-JIAN ,  Ting-Chun WANG ,  Chuan-Pu LIU

IPC: H01L29/45 ,  H01L29/08 ,  H01L29/66 ,  H01L21/768 ,  H01L21/326 ,  H01L21/02 ,  H01L21/285 ,  H01L29/78 ,  H01L29/417 ,  H01L29/165

Abstract: The present disclosure describes a silicide formation process which employs the formation of an amorphous layer in the SiGe S/D region via an application of a substrate bias voltage during a metal deposition process. For example, the method includes a substrate with a gate structure disposed thereon and a source/drain region adjacent to the gate structure. A dielectric is formed over the gate structure and the source-drain region. A contact opening is formed in the dielectric to expose a portion of the gate structure and a portion of the source/drain region. An amorphous layer is formed in the exposed portion of the source/drain region with a thickness and a composition which is based on an adjustable bias voltage applied to the substrate. Further, an anneal is performed to form a silicide on the source/drain region.