SEMICONDUCTOR DEVICE STRUCTURE WITH BARRIER LAYER AND METHOD FOR FORMING THE SAME

    公开(公告)号:US20190148522A1

    公开(公告)日:2019-05-16

    申请号:US16174921

    申请日:2018-10-30

    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric structure over a transistor. The method includes forming a first recess in the dielectric structure. The method includes forming a first barrier layer over a first inner wall of the first recess. The first barrier layer has a first opening over a first portion of the dielectric structure, and the first barrier layer close to a first bottom surface of the first recess is thicker than the first barrier layer close to a top surface of the dielectric structure. The method includes removing the first portion through the first opening to form a second recess in the dielectric structure. The method includes forming a second barrier layer over a second inner wall of the second recess. The method includes forming a contact layer in the first opening and the second opening.

    ELECTROCHEMICAL PLATING SYSTEM AND METHOD OF USING

    公开(公告)号:US20200173051A1

    公开(公告)日:2020-06-04

    申请号:US16677563

    申请日:2019-11-07

    Abstract: An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.

    FLAT STI SURFACE FOR GATE OXIDE UNIFORMITY IN FIN FET DEVICES
    6.
    发明申请
    FLAT STI SURFACE FOR GATE OXIDE UNIFORMITY IN FIN FET DEVICES 有权
    Fin FET器件中的栅极氧化物均匀性的平坦表面

    公开(公告)号:US20170062616A1

    公开(公告)日:2017-03-02

    申请号:US14925846

    申请日:2015-10-28

    Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile by the thermal hydrogen treatment.

    Abstract translation: 制造Fin FET的操作包括提供具有鳍结构的衬底,其中鳍结构的上部具有第一翅片表面轮廓。 隔离区域形成在基板上并与翅片结构接触。 隔离区域的一部分通过蚀刻工艺凹陷以形成凹陷部分并且暴露鳍结构的上部,其中凹部具有第一隔离表面轮廓。 对翅片结构和凹部施加热氢处理。 在翅片结构上形成具有基本上均匀厚度的栅介质层,其中凹部从第一隔离表面轮廓调节到第二隔离表面轮廓,并且翅片结构从第一翅片表面轮廓调节到第二翅片 表面轮廓由热氢处理。

    FLAT STI SURFACE FOR GATE OXIDE UNIFORMITY IN FIN FET DEVICES

    公开(公告)号:US20200152795A1

    公开(公告)日:2020-05-14

    申请号:US16735495

    申请日:2020-01-06

    Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.

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