公开(公告)号：US20190148522A1

公开(公告)日：2019-05-16

申请号：US16174921

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang WU ,  Shiu-Ko JANGJIAN ,  Ting-Chun WANG ,  Yung-Si YU

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L21/285 ,  H01L29/49 ,  H01L21/762

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric structure over a transistor. The method includes forming a first recess in the dielectric structure. The method includes forming a first barrier layer over a first inner wall of the first recess. The first barrier layer has a first opening over a first portion of the dielectric structure, and the first barrier layer close to a first bottom surface of the first recess is thicker than the first barrier layer close to a top surface of the dielectric structure. The method includes removing the first portion through the first opening to form a second recess in the dielectric structure. The method includes forming a second barrier layer over a second inner wall of the second recess. The method includes forming a contact layer in the first opening and the second opening.

公开(公告)号：US20170162395A1

公开(公告)日：2017-06-08

申请号：US15435168

申请日：2017-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Shiu-Ko JANGJIAN ,  Chung-Ren SUN ,  Ming-Te CHEN ,  Ting-Chun WANG ,  Jun-Jie CHENG

IPC: H01L21/28 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor fin, a lining oxide layer, a silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top fin surface, an upper fin side surface portion adjacent to the top fin surface, and a lower fin side surface contiguously connected to the upper fin side surface portion. The lining oxide layer peripherally encloses the lower fin side surface portion of the semiconductor fin. The silicon nitride based layer is disposed conformally over the lining oxide layer. The gate oxide layer is disposed conformally over the top fin surface and the upper fin side surface portion.

公开(公告)号：US20210238765A1

公开(公告)日：2021-08-05

申请号：US17238080

申请日：2021-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun-Nan NIAN ,  Shiu-Ko JANGJIAN ,  Yu-Ren PENG ,  Yao-Hsiang LIANG ,  Ting-Chun WANG

IPC: C25D17/00 ,  C25D21/12 ,  C25D3/38 ,  H01L21/768

Abstract: A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.

公开(公告)号：US20200173051A1

公开(公告)日：2020-06-04

申请号：US16677563

申请日：2019-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jun-Nan Nian ,  Shiu-Ko JANGJIAN ,  Ting-Chun WANG ,  Ing-Ju LEE ,  Yu-Ren PENG ,  Yao-Hsiang LIANG

IPC: C25D17/00 ,  C25D21/12

Abstract: An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.

公开(公告)号：US20170133509A1

公开(公告)日：2017-05-11

申请号：US15415790

申请日：2017-01-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ting HSIAO ,  Cheng-Ta WU ,  Lun-Kuang TAN ,  Liang-Yu YEN ,  Ting-Chun WANG ,  Tsung-Han WU ,  Wei-Ming YOU

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7856 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.

公开(公告)号：US20170062616A1

公开(公告)日：2017-03-02

申请号：US14925846

申请日：2015-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Shiu-Ko JANGJIAN ,  Cheng-Wei CHEN ,  Ting-Chun WANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/7854 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile by the thermal hydrogen treatment.

Abstract translation: 制造Fin FET的操作包括提供具有鳍结构的衬底，其中鳍结构的上部具有第一翅片表面轮廓。 隔离区域形成在基板上并与翅片结构接触。 隔离区域的一部分通过蚀刻工艺凹陷以形成凹陷部分并且暴露鳍结构的上部，其中凹部具有第一隔离表面轮廓。 对翅片结构和凹部施加热氢处理。 在翅片结构上形成具有基本上均匀厚度的栅介质层，其中凹部从第一隔离表面轮廓调节到第二隔离表面轮廓，并且翅片结构从第一翅片表面轮廓调节到第二翅片 表面轮廓由热氢处理。

公开(公告)号：US20170040456A1

公开(公告)日：2017-02-09

申请号：US15332875

申请日：2016-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiu-Ko JANGJIAN ,  Chi-Cherng JENG ,  Chih-Nan WU ,  Chun-Che LIN ,  Ting-Chun WANG

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/161 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02274 ,  H01L21/0228 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an isolation structure formed on the substrate. The fin structure has a top portion and a bottom portion, and the bottom portion is embedded in the isolation structure. The FinFET device structure further includes a protection layer formed on the top portion of the fin structure. An interface is between the protection layer and the top portion of the fin structure, and the interface has a roughness in a range from about 0.1 nm to about 2.0 nm.

Abstract translation: 提供了一种翅片场设备结构及其形成方法。 FinFET器件结构包括从衬底延伸的衬底和鳍结构。 FinFET器件结构还包括形成在衬底上的隔离结构。 翅片结构具有顶部和底部，并且底部嵌入隔离结构中。 FinFET器件结构还包括形成在鳍结构的顶部上的保护层。 界面处于保护层和翅片结构的顶部之间，并且界面的粗糙度在约0.1nm至约2.0nm的范围内。

公开(公告)号：US20200251577A1

公开(公告)日：2020-08-06

申请号：US16852973

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yang WU ,  Shiu-Ko JANGJIAN ,  Ting-Chun WANG ,  Yung-Si YU

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L21/762 ,  H01L21/285 ,  H01L29/49

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a transistor over a substrate. The semiconductor device structure includes a dielectric structure over the substrate and covering the transistor. The semiconductor device structure includes a contact structure passing through the dielectric structure and electrically connected to the transistor. The contact structure includes a contact layer, a first barrier layer, and a second barrier layer, the first barrier layer surrounds the contact layer, the second barrier layer surrounds a first upper portion of the first barrier layer, a first lower portion of the first barrier layer is in direct contact with the dielectric structure, and a thickness of the first lower portion increases toward the substrate.

公开(公告)号：US20200152795A1

公开(公告)日：2020-05-14

申请号：US16735495

申请日：2020-01-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Cheng-Wei CHEN ,  Shiu-Ko JANGJIAN ,  Ting-Chun WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L29/06

Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.

公开(公告)号：US20190198672A1

公开(公告)日：2019-06-27

申请号：US16230025

申请日：2018-12-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta WU ,  Cheng-Wei CHEN ,  Shiu-Ko JANGJIAN ,  Ting-Chun WANG

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/06 ,  H01L29/16 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7854 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848

Abstract: Operations in fabricating a Fin FET include providing a substrate having a fin structure, where an upper portion of the fin structure has a first fin surface profile. An isolation region is formed on the substrate and in contact with the fin structure. A portion of the isolation region is recessed by an etch process to form a recessed portion and to expose the upper portion of the fin structure, where the recessed portion has a first isolation surface profile. A thermal hydrogen treatment is applied to the fin structure and the recessed portion. A gate dielectric layer is formed with a substantially uniform thickness over the fin structure, where the recessed portion is adjusted from the first isolation surface profile to a second isolation surface profile and the fin structure is adjusted from the first fin surface profile to a second fin surface profile, by the thermal hydrogen treatment.