公开(公告)号：US20230155001A1

公开(公告)日：2023-05-18

申请号：US17651347

申请日：2022-02-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Han Chen ,  Shih-Yu Chang ,  Chien-Chih Chiu ,  Huang-Ming Chen ,  Jyu-Horng Shieh

IPC: H01L29/66 ,  H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/76897 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L21/76807 ,  H01L29/41791 ,  H01L21/823475

Abstract: A method includes forming a transistor comprising a source/drain region and a gate electrode, forming a source/drain contact plug over and electrically connecting to the source/drain region, forming a first inter-layer dielectric over the source/drain contact plug, forming an etch stop layer over the first inter-layer dielectric, etching the etch stop layer to form a first via opening, forming a second inter-layer dielectric over the first inter-layer dielectric, performing an etching process, so that the second inter-layer dielectric is etched to form a trench, and the first via opening in the etch stop layer is extended into the first inter-layer dielectric to reveal the source/drain contact plug, and filling the trench and the first via opening in common processes to form a metal line and a via, respectively.

公开(公告)号：US20240387227A1

公开(公告)日：2024-11-21

申请号：US18787978

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yu Chang ,  Chien-Han Chen ,  Chien-Chih Chiu ,  Chi-Che Tseng

IPC: H01L21/683 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/687 ,  H01L21/8238

Abstract: Semiconductor devices, methods of manufacturing the semiconductor device and tools are disclosed herein. Some methods include providing an electrostatic chuck and placing an edge ring adjacent to the electrostatic chuck. The electrostatic chuck includes a first electrode to generate a sheath at a first distance over the electrostatic chuck. The edge ring includes a coil and a second electrode to generate an electric field control to maintain a portion of the sheath over the edge ring in a coplanar orientation with the portion of the sheath over the electrostatic chuck.

公开(公告)号：US20220285216A1

公开(公告)日：2022-09-08

申请号：US17750887

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Han Chen ,  Chien-Chih Chiu ,  Ming-Chung Liang

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02

Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.

公开(公告)号：US12293944B2

公开(公告)日：2025-05-06

申请号：US17750887

申请日：2022-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Han Chen ,  Chien-Chih Chiu ,  Ming-Chung Liang

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/532

Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.

公开(公告)号：US20220367226A1

公开(公告)日：2022-11-17

申请号：US17520301

申请日：2021-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yu Chang ,  Chien-Han Chen ,  Chien-Chih Chiu ,  Chi-Che Tseng

IPC: H01L21/683 ,  H01L21/687 ,  H01L21/67

Abstract: Semiconductor devices, methods of manufacturing the semiconductor device and tools are disclosed herein. Some methods include providing an electrostatic chuck and placing an edge ring adjacent to the electrostatic chuck. The electrostatic chuck includes a first electrode to generate a sheath at a first distance over the electrostatic chuck. The edge ring includes a coil and a second electrode to generate an electric field control to maintain a portion of the sheath over the edge ring in a coplanar orientation with the portion of the sheath over the electrostatic chuck.