公开(公告)号：US20150228794A1

公开(公告)日：2015-08-13

申请号：US14179585

申请日：2014-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Hung Pin Chen ,  Wei-Barn Chen ,  Chih-Fu Chang ,  Chih-Kang Chao ,  Ling-Sung Wang

IPC: H01L29/78

CPC classification number: H01L29/7853 ,  H01L21/823431 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/78642

Abstract: As will be appreciated in more detail herein, the present disclosure provides for FinFET techniques whereby a FinFET channel region has a particular orientation with respect to the crystalline lattice of the semiconductor device to provide enhanced mobility, compared to conventional FinFETs. In particular, the present disclosure provides FinFETs with a channel region whose lattice includes silicon atoms arranged on (551) lattice plane. In this configuration, the sidewalls of the channel region are particularly smooth at the atomic level, which tends to promote higher carrier mobility and higher device performance than previously achievable.

Abstract translation: 如本文将更详细地理解的，本公开提供FinFET技术，由此与常规FinFET相比，FinFET沟道区相对于半导体器件的晶格具有特定取向以提供增强的迁移率。 特别地，本公开为FinFET提供其晶格包括布置在（551）晶格平面上的硅原子的沟道区。 在这种配置中，沟道区的侧壁在原子水平上特别平滑，这倾向于促进比以前可实现的更高的载流子迁移率和更高的器件性能。

公开(公告)号：US09209304B2

公开(公告)日：2015-12-08

申请号：US14179585

申请日：2014-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Hung Pin Chen ,  Wei-Barn Chen ,  Chih-Fu Chang ,  Chih-Kang Chao ,  Ling-Sung Wang

IPC: H01L29/78

CPC classification number: H01L29/7853 ,  H01L21/823431 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/78642

Abstract: As will be appreciated in more detail herein, the present disclosure provides for FinFET techniques whereby a FinFET channel region has a particular orientation with respect to the crystalline lattice of the semiconductor device to provide enhanced mobility, compared to conventional FinFETs. In particular, the present disclosure provides FinFETs with a channel region whose lattice includes silicon atoms arranged on (551) lattice plane. In this configuration, the sidewalls of the channel region are particularly smooth at the atomic level, which tends to promote higher carrier mobility and higher device performance than previously achievable.

Abstract translation: 如本文将更详细地理解的，本公开提供FinFET技术，由此与常规FinFET相比，FinFET沟道区相对于半导体器件的晶格具有特定取向以提供增强的迁移率。 特别地，本公开为FinFET提供其晶格包括布置在（551）晶格平面上的硅原子的沟道区。 在这种配置中，沟道区的侧壁在原子水平上特别平滑，这倾向于促进比以前可实现的更高的载流子迁移率和更高的器件性能。

公开(公告)号：US09171759B2

公开(公告)日：2015-10-27

申请号：US13717883

申请日：2012-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Pin Cheng ,  Jung-Liang Chien ,  Chih-Kang Chao ,  Chi-Cherng Jeng ,  Hsin-Chi Chen ,  Ying-Lang Wang

IPC: H01L21/78 ,  H01L23/00 ,  H01L23/58 ,  H01L21/66

CPC classification number: H01L21/78 ,  H01L22/32 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/00

Abstract: A semiconductor wafer having a plurality of chip die areas arranged on a wafer in an array, each chip die area including a seal ring area with one or more first sets of polygonal structures. The wafer further comprises scribe line areas between the chip die areas, the scribe line areas including one or more second sets of polygonal structures. The presence of proximate polygonal structures between the scribe line and seal ring areas balance stresses between the chip die areas during wafer dicing operation.

Abstract translation: 一种半导体晶片，具有排列在阵列中的晶片上的多个芯片晶粒区域，每个芯片晶粒区域包括具有一个或多个第一组多边形结构的密封环区域。 晶片还包括在芯片模具区域之间的划线区域，划线区域包括一个或多个第二组多边形结构。 切割线和密封环区域之间的近似多边形结构的存在在晶片切割操作期间平衡芯片晶片区域之间的应力。