中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.015 seconds)

    Asymmetric gate pitch
    1.
    发明授权
    Asymmetric gate pitch 有权

    公开(公告)号：US10957695B2

    公开(公告)日：2021-03-23

    申请号：US16657528

    申请日：2019-10-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Barn Chen ,  Chi-Cherng Jeng ,  Shiu-Ko Jangjian ,  Ting-Huang Kuo

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06

    Abstract: The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures.

    N/P MOS FINFET PERFORMANCE ENHANCEMENT BY SPECIFIC ORIENTATION SURFACE
    2.
    发明申请
    N/P MOS FINFET PERFORMANCE ENHANCEMENT BY SPECIFIC ORIENTATION SURFACE 有权
    N / P MOS FinFET性能通过特定方位表面增强

    公开(公告)号：US20150228794A1

    公开(公告)日：2015-08-13

    申请号：US14179585

    申请日：2014-02-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ru-Shang Hsiao ,  Hung Pin Chen ,  Wei-Barn Chen ,  Chih-Fu Chang ,  Chih-Kang Chao ,  Ling-Sung Wang

    IPC: H01L29/78

    CPC classification number: H01L29/7853 ,  H01L21/823431 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/78642

    Abstract: As will be appreciated in more detail herein, the present disclosure provides for FinFET techniques whereby a FinFET channel region has a particular orientation with respect to the crystalline lattice of the semiconductor device to provide enhanced mobility, compared to conventional FinFETs. In particular, the present disclosure provides FinFETs with a channel region whose lattice includes silicon atoms arranged on (551) lattice plane. In this configuration, the sidewalls of the channel region are particularly smooth at the atomic level, which tends to promote higher carrier mobility and higher device performance than previously achievable.

    Abstract translation: 如本文将更详细地理解的，本公开提供FinFET技术，由此与常规FinFET相比，FinFET沟道区相对于半导体器件的晶格具有特定取向以提供增强的迁移率。 特别地，本公开为FinFET提供其晶格包括布置在（551）晶格平面上的硅原子的沟道区。 在这种配置中，沟道区的侧壁在原子水平上特别平滑，这倾向于促进比以前可实现的更高的载流子迁移率和更高的器件性能。

    Asymmetric gate pitch
    4.
    发明授权
    Asymmetric gate pitch 有权

    公开(公告)号：US10475790B2

    公开(公告)日：2019-11-12

    申请号：US15885596

    申请日：2018-01-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Barn Chen ,  Chi-Cherng Jeng ,  Shiu-Ko Jangjian ,  Ting-Huang Kuo

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06

    Abstract: The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures.

    Semiconductor device having planar transistor and FinFET
    6.
    发明授权
    Semiconductor device having planar transistor and FinFET 有权

    公开(公告)号：US11328958B2

    公开(公告)日：2022-05-10

    申请号：US17079052

    申请日：2020-10-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Barn Chen ,  Ting-Huang Kuo ,  Shiu-Ko Jangjian ,  Chi-Cherng Jeng ,  Kuang-Yao Lo

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L21/265 ,  H01L27/088 ,  H01L29/08

    Abstract: A device includes first and second transistors and first and second isolation structures. The first transistor includes a raised structure, a first gate structure over the raised structure, and a first source/drain structure over the raised structure and adjacent the first gate structure. The first isolation structure surrounds the raised structure and the first source/drain structure of the first transistor. A bottommost surface of the first source/drain structure is spaced apart from a topmost surface of the first isolation structure. The second transistor includes a fin structure, a second gate structure over the raised structure, and a second source/drain structure over the fin structure. The second isolation structure surrounds a bottom of the fin structure of the second transistor. A bottommost surface of the second source/drain structure is in contact with a topmost surface of the second isolation structure.

    Semiconductor device having planar transistor and FinFET
    7.
    发明授权
    Semiconductor device having planar transistor and FinFET 有权

    公开(公告)号：US10818555B2

    公开(公告)日：2020-10-27

    申请号：US16687605

    申请日：2019-11-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Barn Chen ,  Ting-Huang Kuo ,  Shiu-Ko Jangjian ,  Chi-Cherng Jeng ,  Kuang-Yao Lo

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L21/265 ,  H01L27/088 ,  H01L29/08

    Abstract: A device includes first and second transistors and first and second isolation structures. The first transistor includes an active region including a first channel region, a first source and a first drain in the active region and respectively on opposite sides of the first channel region, and a first gate structure over the first channel region. The first isolation structure surrounds the active region of the first transistor. The second transistor includes a second source and a second drain, a fin structure includes a second channel region between the second source and the second drain, and a second gate structure over the second channel region. The second isolation structure surrounds a bottom portion of the fin structure of the second transistor. The top of the first isolation structure is higher than a top of the second isolation structure.

    ASYMMETRIC GATE PITCH
    8.
    发明申请
    ASYMMETRIC GATE PITCH 审中-公开

    公开(公告)号：US20190096883A1

    公开(公告)日：2019-03-28

    申请号：US15885596

    申请日：2018-01-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wei-Barn Chen ,  Chi-Cherng Jeng ,  Shiu-Ko Jangjian ,  Ting-Huang Kuo

    IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234

    Abstract: The present disclosure describes an exemplary asymmetric CPP layout for a semiconductor structure with a different gate pitch over the source and the drain regions to mitigate gate-to-gate parasitic capacitances over the drain region, thus improving cutoff frequency. For example, the semiconductor structure can include a fin on a substrate. The semiconductor structure can also include first and second gate structures formed on the fin and separated by a first space. The semiconductor structure can also include a third gate structure formed on the fin between the first and the second gate structures. The third gate structure can be separated from the first gate structure by a second pitch and separated from the second gate structure by a third pitch that is greater than the second pitch. The semiconductor structure further includes a source region formed between the first and third gate structures, and a drain region formed between the third and the second gate structures.

    Method for manufacturing dual FinFET device
    10.
    发明授权
    Method for manufacturing dual FinFET device 有权

    公开(公告)号：US10483167B2

    公开(公告)日：2019-11-19

    申请号：US15678097

    申请日：2017-08-15

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Barn Chen ,  Ting-Huang Kuo ,  Shiu-Ko Jangjian ,  Chi-Cherng Jeng ,  Kuang-Yao Lo

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/308 ,  H01L21/265 ,  H01L27/088

    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A hard mask and a mask layer are formed on a first region and a second region of the substrate. The substrate is recessed using the hard mask and the mask layer to form a fin structure in the first region and a raised structure in the second region. First isolation structures and second isolation structures are formed on lower portions of opposite sidewalls of the fin structure and opposite sidewalls of the raised structure. A first gate structure is formed on a portion of the fin structure, and a second gate structure is formed on a portion of the raised structure. A first source and a first drain are formed on opposite sides of the first gate structure, and a second source and a second drain are formed on opposite sides of the second gate structure.

Patent Agency Ranking