公开(公告)号：US20150228794A1

公开(公告)日：2015-08-13

申请号：US14179585

申请日：2014-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Hung Pin Chen ,  Wei-Barn Chen ,  Chih-Fu Chang ,  Chih-Kang Chao ,  Ling-Sung Wang

IPC: H01L29/78

CPC classification number: H01L29/7853 ,  H01L21/823431 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/78642

Abstract: As will be appreciated in more detail herein, the present disclosure provides for FinFET techniques whereby a FinFET channel region has a particular orientation with respect to the crystalline lattice of the semiconductor device to provide enhanced mobility, compared to conventional FinFETs. In particular, the present disclosure provides FinFETs with a channel region whose lattice includes silicon atoms arranged on (551) lattice plane. In this configuration, the sidewalls of the channel region are particularly smooth at the atomic level, which tends to promote higher carrier mobility and higher device performance than previously achievable.

Abstract translation: 如本文将更详细地理解的，本公开提供FinFET技术，由此与常规FinFET相比，FinFET沟道区相对于半导体器件的晶格具有特定取向以提供增强的迁移率。 特别地，本公开为FinFET提供其晶格包括布置在（551）晶格平面上的硅原子的沟道区。 在这种配置中，沟道区的侧壁在原子水平上特别平滑，这倾向于促进比以前可实现的更高的载流子迁移率和更高的器件性能。

公开(公告)号：US09209304B2

公开(公告)日：2015-12-08

申请号：US14179585

申请日：2014-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ru-Shang Hsiao ,  Hung Pin Chen ,  Wei-Barn Chen ,  Chih-Fu Chang ,  Chih-Kang Chao ,  Ling-Sung Wang

IPC: H01L29/78

CPC classification number: H01L29/7853 ,  H01L21/823431 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/78642

Abstract: As will be appreciated in more detail herein, the present disclosure provides for FinFET techniques whereby a FinFET channel region has a particular orientation with respect to the crystalline lattice of the semiconductor device to provide enhanced mobility, compared to conventional FinFETs. In particular, the present disclosure provides FinFETs with a channel region whose lattice includes silicon atoms arranged on (551) lattice plane. In this configuration, the sidewalls of the channel region are particularly smooth at the atomic level, which tends to promote higher carrier mobility and higher device performance than previously achievable.

Abstract translation: 如本文将更详细地理解的，本公开提供FinFET技术，由此与常规FinFET相比，FinFET沟道区相对于半导体器件的晶格具有特定取向以提供增强的迁移率。 特别地，本公开为FinFET提供其晶格包括布置在（551）晶格平面上的硅原子的沟道区。 在这种配置中，沟道区的侧壁在原子水平上特别平滑，这倾向于促进比以前可实现的更高的载流子迁移率和更高的器件性能。

公开(公告)号：US09929268B2

公开(公告)日：2018-03-27

申请号：US15099607

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chii-Ming Wu ,  Ru-Shang Hsiao ,  Hung Pin Chen ,  Sen-Hong Syue ,  Chi-Cherng Jeng

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method of fabricating a FinFET includes at last the following steps. A direction is determined by tilting 8.05±2 degrees from a normal vector of a (110) lattice plane of a semiconductor substrate. The semiconductor substrate is patterned along a lattice plane perpendicular to the direction, so as to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin having sidewalls disposed on a (551) lattice plane. Insulators are in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. Strained material portions are formed over the semiconductor fins revealed by the gate stack.

公开(公告)号：US20170301793A1

公开(公告)日：2017-10-19

申请号：US15099607

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chii-Ming Wu ,  Ru-Shang Hsiao ,  Hung Pin Chen ,  Sen-Hong Syue ,  Chi-Cherng Jeng

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method of fabricating a FinFET includes at last the following steps. A direction is determined by tilting 8.05±2 degrees from a normal vector of a (110) lattice plane of a semiconductor substrate. The semiconductor substrate is patterned along a lattice plane perpendicular to the direction, so as to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin having sidewalls disposed on a (551) lattice plane. Insulators are in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. Strained material portions are formed over the semiconductor fins revealed by the gate stack.