公开(公告)号：US20230307292A1

公开(公告)日：2023-09-28

申请号：US18317759

申请日：2023-05-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chiang CHEN ,  Chun-Ting WU ,  Ching-Hou SU ,  Chih-Pin WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L21/76832 ,  H01L23/5226 ,  H01L21/76834 ,  H01L21/02274 ,  H01L24/13 ,  H01L24/11 ,  H01L2224/13024 ,  H01L2224/0401 ,  H01L2224/02381

Abstract: An integrated circuit (IC) structure includes a substrate, an interconnect structure, metal lines, a liner, a protecting layer, and a nitride-free passivation layer. The interconnect structure is over the substrate. The metal lines are over the interconnect structure. The liner is conformally formed on the metal lines. The protecting layer is over the liner. The nitride-free passivation layer continuously extends from the liner to the protecting layer and forms an interface with the liner.

公开(公告)号：US20250112032A1

公开(公告)日：2025-04-03

申请号：US18981170

申请日：2024-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Jen YANG ,  Yi-Zhen CHEN ,  Chih-Pin WANG ,  Chao-Li SHIH ,  Ching-Hou SU ,  Cheng-Yi HUANG

IPC: H01J37/34 ,  C23C14/35

Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.

公开(公告)号：US20200161108A1

公开(公告)日：2020-05-21

申请号：US16596109

申请日：2019-10-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Jen YANG ,  Yi-Zhen CHEN ,  Chih-Pin WANG ,  Chao-Li SHIH ,  Ching-Hou SU ,  Cheng-Yi HUANG

IPC: H01J37/34 ,  C23C14/35

Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.

公开(公告)号：US20240087861A1

公开(公告)日：2024-03-14

申请号：US18513313

申请日：2023-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Jen YANG ,  Yi-Zhen CHEN ,  Chih-Pin WANG ,  Chao-Li SHIH ,  Ching-Hou SU ,  Cheng-Yi HUANG

IPC: H01J37/34 ,  C23C14/35

CPC classification number: H01J37/3408 ,  C23C14/35 ,  H01J37/3458 ,  H01J2237/152

Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.

公开(公告)号：US20220367160A1

公开(公告)日：2022-11-17

申请号：US17876422

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Jen YANG ,  Yi-Zhen CHEN ,  Chih-Pin WANG ,  Chao-Li SHIH ,  Ching-Hou SU ,  Cheng-Yi HUANG

IPC: H01J37/34 ,  C23C14/35

Abstract: In an embodiment, a magnetic assembly includes: an inner permeance annulus; and an outer permeance annulus connected to the inner permeance annulus via magnets, wherein the outer permeance annulus comprises a peak region with a thickness greater than other regions of the outer permeance annulus.

公开(公告)号：US20210343587A1

公开(公告)日：2021-11-04

申请号：US17378566

申请日：2021-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chiang CHEN ,  Chun-Ting WU ,  Ching-Hou SU ,  Chih-Pin WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L23/00

Abstract: An integrated circuit (IC) structure includes a substrate, a transistor, an interconnect structure, a plurality of metal lines, an oxide liner, a passivation layer, and a nitride layer. The transistor is on the substrate. The interconnect structure is over the transistor. The metal lines is on the interconnect structure. The oxide liner is over the plurality of metal lines. The passivation layer is over the oxide liner and is more porous than the passivation layer. The nitride layer is over the passivation layer.

公开(公告)号：US20210217659A1

公开(公告)日：2021-07-15

申请号：US16744014

申请日：2020-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chiang CHEN ,  Chun-Ting WU ,  Ching-Hou SU ,  Chih-Pin WANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/02 ,  H01L23/00

Abstract: A method includes forming metal lines over an interconnect structure that is formed above transistors; depositing a liner layer over the metal lines using a first high density plasma chemical vapor deposition (HDPCVD) process with a zero RF bias power depositing a first passivation layer over the liner layer using a second HDPCVD process with a non-zero RF bias power; and depositing a second passivation layer in contact with a top surface of the first passivation layer using a third HDPCVD process with a non-zero RF bias power.