公开(公告)号：US20210366802A1

公开(公告)日：2021-11-25

申请号：US16881004

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hui Huang ,  Shang-Yun Hou ,  Tien-Yu Huang ,  Heh-Chang Huang ,  Kuan-Yu Huang ,  Shu-Chia Hsu ,  Yu-Shun Lin

IPC: H01L23/31 ,  H01L25/16

Abstract: A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.

公开(公告)号：US20180138056A1

公开(公告)日：2018-05-17

申请号：US15855305

申请日：2017-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L21/50 ,  H01L31/09 ,  H01L31/0232 ,  H01L27/146 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H01L21/311 ,  H01L23/48 ,  H01L23/31 ,  H01L23/29 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L21/563 ,  H01L21/31111 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/82 ,  H01L25/167 ,  H01L25/50 ,  H01L27/14618 ,  H01L31/0232 ,  H01L31/09 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad over a first chip and a second conductive pad over a second chip. A molding structure surrounds the first chip and the second chip. A first passivation layer is over the first chip and the second chip, and a conductive structure is over the first passivation layer. The conductive structure is coupled to the first conductive pad. A second passivation layer is over the conductive structure. The first passivation layer and the second passivation layer have sidewalls defining an aperture that is directly over an optical element within the second chip and that extends through the first passivation layer and the second passivation layer.

公开(公告)号：US20160343697A1

公开(公告)日：2016-11-24

申请号：US15223609

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L21/768 ,  H01L21/311 ,  H01L23/29 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/31111 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/82 ,  H01L25/167 ,  H01L25/50 ,  H01L27/14618 ,  H01L31/0232 ,  H01L31/09 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.

公开(公告)号：US11694939B2

公开(公告)日：2023-07-04

申请号：US16881004

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hui Huang ,  Shang-Yun Hou ,  Tien-Yu Huang ,  Heh-Chang Huang ,  Kuan-Yu Huang ,  Shu-Chia Hsu ,  Yu-Shun Lin

IPC: H01L23/31 ,  H01L25/16

CPC classification number: H01L23/3185 ,  H01L25/167

Abstract: A semiconductor package includes a substrate, a stacked structure, an encapsulation material, a lid structure, and a coupler. The stacked structure is disposed over and bonded to the substrate. The encapsulation material partially encapsulates the stacked structure. The lid structure is disposed on the substrate, wherein the lid structure surrounds the stacked structure and covers a top surface of the stacked structure. The coupler is bonded to the stacked structure, wherein a portion of the coupler penetrates through and extends out of the lid structure.

公开(公告)号：US20190237379A1

公开(公告)日：2019-08-01

申请号：US16382542

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/31 ,  H01L33/48 ,  H01L21/56 ,  H01L21/311 ,  H01L21/48 ,  H01L21/50 ,  H01L31/09 ,  H01L31/0232 ,  H01L31/0203 ,  H01L27/146 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H01L23/538 ,  H01L23/485 ,  H01L23/48 ,  H01L23/29 ,  H01L23/28 ,  H01L21/768 ,  H01L21/683 ,  H01L33/52

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad disposed over a first substrate and a second conductive pad disposed over a second substrate. The second conductive pad is a multi-layer structure having an uppermost metal layer including titanium or nickel. A molding structure surrounds the first substrate and the second substrate. A conductive structure is over the first substrate and the second substrate. The conductive structure is conductively coupled to the second conductive pad.

公开(公告)号：US10276471B2

公开(公告)日：2019-04-30

申请号：US15855305

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/31 ,  H01L23/48 ,  H01L21/50 ,  H01L31/0232 ,  H01L31/09 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L31/0203 ,  H01L33/52 ,  H01L33/48 ,  H01L23/28 ,  H01L23/485 ,  H01L23/00 ,  H01L27/146 ,  H01L21/311 ,  H01L21/683 ,  H01L21/768 ,  H01L23/29 ,  H01L25/16 ,  H01L25/00

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad over a first chip and a second conductive pad over a second chip. A molding structure surrounds the first chip and the second chip. A first passivation layer is over the first chip and the second chip, and a conductive structure is over the first passivation layer. The conductive structure is coupled to the first conductive pad. A second passivation layer is over the conductive structure. The first passivation layer and the second passivation layer have sidewalls defining an aperture that is directly over an optical element within the second chip and that extends through the first passivation layer and the second passivation layer.

公开(公告)号：US10748825B2

公开(公告)日：2020-08-18

申请号：US16382542

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/31 ,  H01L23/48 ,  H01L21/50 ,  H01L31/0232 ,  H01L31/09 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L31/0203 ,  H01L33/52 ,  H01L33/48 ,  H01L23/28 ,  H01L23/485 ,  H01L23/00 ,  H01L27/146 ,  H01L33/54 ,  H01L21/311 ,  H01L21/683 ,  H01L21/768 ,  H01L23/29 ,  H01L25/16 ,  H01L25/00

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad disposed over a first substrate and a second conductive pad disposed over a second substrate. The second conductive pad is a multi-layer structure having an uppermost metal layer including titanium or nickel. A molding structure surrounds the first substrate and the second substrate. A conductive structure is over the first substrate and the second substrate. The conductive structure is conductively coupled to the second conductive pad.

公开(公告)号：US09865481B2

公开(公告)日：2018-01-09

申请号：US15223609

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/56 ,  H01L23/48 ,  H01L21/50 ,  H01L23/31 ,  H01L31/0232 ,  H01L31/09 ,  H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L27/146 ,  H01L21/311 ,  H01L21/683 ,  H01L21/768 ,  H01L23/29 ,  H01L25/16 ,  H01L25/00

CPC classification number: H01L21/563 ,  H01L21/31111 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/82 ,  H01L25/167 ,  H01L25/50 ,  H01L27/14618 ,  H01L31/0232 ,  H01L31/09 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.