公开(公告)号：US20200125782A1

公开(公告)日：2020-04-23

申请号：US16721255

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Cheng Hsiao ,  Chang-Yu Huang ,  Juan Yi Chen ,  Ke-Wei Su ,  Chung-Kai Lin ,  Lester Chang ,  Min-Chie Jeng

IPC: G06F30/39 ,  G06F7/58 ,  G06F30/367

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

公开(公告)号：US20200075074A1

公开(公告)日：2020-03-05

申请号：US16122057

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Chung Te Lin ,  Min Cao ,  Yuh-Jier Mii ,  Sheng-Chih Lai

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has an operative magnetic tunnel junction (MTJ) device configured to store a data state. The operative MTJ device is coupled to a bit-line. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus has one or more regulating MTJ devices that are configured to control a current provided to the operative MTJ device.

公开(公告)号：US20240251566A1

公开(公告)日：2024-07-25

申请号：US18627334

申请日：2024-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Yen-Chung Ho ,  Pin-Cheng Hsu ,  Han-Ting Tsai ,  Katherine Chiang

IPC: H10B61/00 ,  G06F3/06 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/20 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  H10N50/01 ,  H10N50/80

Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.

公开(公告)号：US11133044B2

公开(公告)日：2021-09-28

申请号：US15995578

申请日：2018-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Chung-Te Lin ,  Min Cao ,  Randy Osborne

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02

Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit includes a first memory device and a second memory device arranged over a substrate. The first memory device is coupled to a first bit-line. The second memory device is coupled to a second bit-line. A shared control element is arranged within the substrate and is configured to provide access to the first memory device and to separately provide access to the second memory device. The shared control element includes one or more control devices sharing one or more components.

公开(公告)号：US11968843B2

公开(公告)日：2024-04-23

申请号：US16270484

申请日：2019-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Yen-Chung Ho ,  Pin-Cheng Hsu ,  Han-Ting Tsai ,  Katherine Chiang

IPC: G06F3/00 ,  G06F3/06 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/20 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  H10N50/01 ,  H10N50/80

Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.

公开(公告)号：US10860769B2

公开(公告)日：2020-12-08

申请号：US16721255

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Cheng Hsiao ,  Chang-Yu Huang ,  Juan Yi Chen ,  Ke-Wei Su ,  Chung-Kai Lin ,  Lester Chang ,  Min-Chie Jeng

IPC: G06F30/39 ,  G06F30/367 ,  G06F7/58

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

公开(公告)号：US20200006423A1

公开(公告)日：2020-01-02

申请号：US16270484

申请日：2019-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Te Lin ,  Yen-Chung Ho ,  Pin-Cheng Hsu ,  Han-Ting Tsai ,  Katherine Chiang

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12 ,  G06F3/06

Abstract: An embodiment of an integrated circuit chip includes a combination processing core and magnetoresistive random access memory (MRAM) circuitry integrated into the chip. The MRAM circuitry includes a plurality of MRAM cells. The MRAM cells are organized into a number of memories, including a cache memory, a main or working memory and an optional secondary storage memory. The cache memory includes multiple cache levels.

公开(公告)号：US10521538B2

公开(公告)日：2019-12-31

申请号：US15335091

申请日：2016-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Cheng Hsiao ,  Chang-Yu Huang ,  Juan Yi Chen ,  Ke-Wei Su ,  Chung-Kai Lin ,  Lester Chang ,  Min-Chie Jeng

IPC: H01J37/32 ,  G06F17/50 ,  G06F7/58

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

公开(公告)号：US11094361B2

公开(公告)日：2021-08-17

申请号：US16122057

申请日：2018-09-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Chung Te Lin ,  Min Cao ,  Yuh-Jier Mii ,  Sheng-Chih Lai

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10

Abstract: In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has an operative magnetic tunnel junction (MTJ) device configured to store a data state. The operative MTJ device is coupled to a bit-line. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus has one or more regulating MTJ devices that are configured to control a current provided to the operative MTJ device.

公开(公告)号：US20170316138A1

公开(公告)日：2017-11-02

申请号：US15335091

申请日：2016-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Cheng Hsiao ,  Chang-Yu Huang ,  Juan Yi Chen ,  Ke-Wei Su ,  Chung-Kai Lin ,  Lester Chang ,  Min-Chie Jeng

IPC: G06F17/50 ,  G06F7/58

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.