公开(公告)号：US20240387451A1

公开(公告)日：2024-11-21

申请号：US18786265

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-I Chu ,  Han-De Chen ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01J37/32 ,  H01L21/02 ,  H01L21/26

Abstract: Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.

公开(公告)号：US20230063975A1

公开(公告)日：2023-03-02

申请号：US17459509

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Chen Teng ,  Chen-Fong Tsai ,  Han-De Chen ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L29/423 ,  H01L29/417 ,  H01L29/40 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L21/67

Abstract: A method of forming a semiconductor device includes loading a first wafer and a second wafer into a wafer bonding system. A relative humidity within the wafer bonding system is measured a first time. After measuring the relative humidity, the relative humidity within the wafer bonding system may be adjusted to be within a desired range. When the relative humidity is within the desired range, the first wafer is bonded to the second wafer.

公开(公告)号：US20220406621A1

公开(公告)日：2022-12-22

申请号：US17479467

申请日：2021-09-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huicheng Chang ,  Jyh-Cherng Sheu ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Yee-Chia Yeo

IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.

公开(公告)号：US12249592B2

公开(公告)日：2025-03-11

申请号：US17648236

申请日：2022-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-De Chen ,  Cheng-I Chu ,  Yun Chen Teng ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/00 ,  H01L21/66 ,  H01L23/00

Abstract: A method includes placing a first wafer on a first wafer stage, placing a second wafer on a second wafer stage, and pushing a center portion of the first wafer to contact the second wafer. A bonding wave propagates from the center portion to edge portions of the first wafer and the second wafer. When the bonding wave propagates from the center portion to the edge portions of the first wafer and the second wafer, a stage gap between the top wafer stage and the bottom wafer stage is reduced.

公开(公告)号：US12237211B2

公开(公告)日：2025-02-25

申请号：US17377667

申请日：2021-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh Chang ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/762 ,  H01L21/67

Abstract: A method of forming a semiconductor device includes mounting a bottom wafer on a bottom chuck and mounting a top wafer on a top chuck, wherein one of the bottom chuck and the top chuck has a gasket. The top chuck is moved towards the bottom chuck. The gasket forms a sealed region between the bottom chuck and the top chuck around the top wafer and the bottom wafer. An ambient pressure in the sealed region is adjusted. The top wafer is bonded to the bottom wafer.

公开(公告)号：US20240153786A1

公开(公告)日：2024-05-09

申请号：US18410100

申请日：2024-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huicheng Chang ,  Jyh-Cherng Sheu ,  Chen-Fong Tsai ,  Yun Chen Teng ,  Han-De Chen ,  Yee-Chia Yeo

IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L25/0652 ,  H01L25/50

Abstract: A method includes bonding a package component to a composite carrier. The composite carrier includes a base carrier and an absorption layer, and the absorption layer is between the base carrier and the package component. A laser beam is projected onto the composite carrier. The laser beam penetrates through the base carrier to ablate the absorption layer. The base carrier may then be separated from the package component.

公开(公告)号：US20230378001A1

公开(公告)日：2023-11-23

申请号：US18365654

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsai-Yu Huang ,  Han-De Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/764

CPC classification number: H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L21/823821 ,  H01L29/42392 ,  H01L29/78696 ,  H01L21/764 ,  H01L29/0673

Abstract: In an embodiment, a device includes: a first semiconductor strip over a substrate, the first semiconductor strip including a first channel region; a second semiconductor strip over the substrate, the second semiconductor strip including a second channel region; a dielectric strip disposed between the first semiconductor strip and the second semiconductor strip, a width of the dielectric strip decreasing along a first direction extending away from the substrate, the dielectric strip including a void; and a gate structure extending along the first channel region, along the second channel region, and along a top surface and sidewalls of the dielectric strip.

公开(公告)号：US20230067346A1

公开(公告)日：2023-03-02

申请号：US17412768

申请日：2021-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-De Chen ,  Yun Chen Teng ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01L21/683

Abstract: In an embodiment, a wafer bonding system includes a chamber, a gas inlet and a gas outlet configured to control a pressure of the chamber to be in a range from 1×10−2 mbar to 1520 torr, a first wafer chuck having a first surface to support a first wafer, and a second wafer chuck having a second surface to support a second wafer, the second surface being opposite the first surface, the second wafer chuck and the first wafer chuck being movable relative to each other, wherein the second surface that supports the second wafer is divided into zones, wherein a vacuum pressure of each zone is controlled independently of other zones.

公开(公告)号：US12211820B2

公开(公告)日：2025-01-28

申请号：US17472086

申请日：2021-09-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-I Chu ,  Han-De Chen ,  Chen-Fong Tsai ,  Jyh-Cherng Sheu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L23/00 ,  H01J37/32 ,  H01L21/02 ,  H01L21/26

Abstract: Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.

公开(公告)号：US20250006687A1

公开(公告)日：2025-01-02

申请号：US18345248

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zheng-Yong Liang ,  Wei-Ting Yeh ,  Han-De Chen ,  Chen-Fong Tsai ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L23/00 ,  H01L23/373

Abstract: An integrated circuit die with two material layers having metal nano-particles and the method of forming the same are provided. The integrated circuit die includes a device layer comprising a first transistor, a first interconnect structure on a first side of the device layer, a first material layer on the first interconnect structure, wherein the first material layer comprises first metal nano-particles, and a second material layer bonded to the first material layer, wherein the second material layer comprises second metal nano-particles, and wherein the first material layer and the second material layer share an interface.