公开(公告)号：US20180308847A1

公开(公告)日：2018-10-25

申请号：US15492508

申请日：2017-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hau-Yan LU ,  Shih-Hsien CHEN ,  Chun-Yao KO ,  Felix Ying-Kit TSUI

IPC: H01L27/105 ,  H01L23/532 ,  H01L23/528 ,  H01L49/02 ,  H01L27/06 ,  H01L27/02

CPC classification number: H01L27/0629 ,  H01L27/11524 ,  H01L28/60 ,  H01L29/42324 ,  H01L29/94

Abstract: A memory system is provided. The memory system includes a number of memory cells and a number of bit lines. The memory cells are interlocked with each other in rows and columns. The memory cells include respective capacitors, respective first transistors and respective second transistors. Respective upper plates of the respective capacitors are electrically connected to respective gates of the respective first transistors, and respective drains of the respective second transistors are connected to respective sources of the respective first transistors. The bit lines are arranged along an extending direction of the rows. Respective bit lines are connected to the respective first transistors through respective bit-line contacts, and each of the respective bit-line contacts is shared by two adjacent memory cells of the extending direction of the rows.

公开(公告)号：US20150098266A1

公开(公告)日：2015-04-09

申请号：US14048873

申请日：2013-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Hsien CHEN ,  Hau-Yan LU ,  Liang-Tai KUO ,  Chun-Yao KO ,  Felix Ying-Kit TSUI

IPC: H01L27/108 ,  G11C11/401

CPC classification number: G11C11/401 ,  G06F3/0625 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3418 ,  H01L27/11558

Abstract: Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation.

Abstract translation: 提供了存储单元及其操作方法。 存储器件包括多个存储器单元。 每个存储单元包括第一晶体管，开关和电容器。 第一晶体管具有连接到相应位线的漏极。 开关具有连接到第一晶体管的源极的第一端子和耦合到参考电压的第二端子。 电容器具有第一板和第二板，并且电容器的第一板电连接到第一晶体管的栅极。 电容器的第二板连接到相应的字线。 当存储单元未被选择执行写入操作或读取操作时，开关被关闭。