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    SEMICONDUCTOR STRUCTURE
    1.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权
    半导体结构

    公开(公告)号：US20160104660A1

    公开(公告)日：2016-04-14

    申请号：US14963235

    申请日：2015-12-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Alexander KALNITSKY ,  Hsiao-Chin TUAN ,  Shih-Fen HUANG ,  Hsin-Li CHENG ,  Felix Ying-Kit TSUI

    IPC: H01L23/48 ,  H01L23/528

    CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.

    Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括具有顶表面和底表面的晶片衬底，以及通过晶片衬底的顶表面和底表面由深沟槽绝缘体限定的晶片衬底中的导电柱。 制造半导体结构的方法包括以下步骤。 从晶片衬底的顶表面形成深沟槽以在晶片衬底中限定导电区域。 导电区域掺杂有掺杂剂。 深沟槽填充有绝缘材料以形成深沟槽绝缘体。 并且晶片衬底从晶片衬底的底表面变薄以暴露深沟槽绝缘体并隔离导电区域以形成导电柱。

    BIOLOGICAL DEVICE AND BIOSENSING METHOD THEREOF
    3.
    发明申请
    BIOLOGICAL DEVICE AND BIOSENSING METHOD THEREOF 审中-公开
    生物装置及其生物传感方法

    公开(公告)号：US20160320335A1

    公开(公告)日：2016-11-03

    申请号：US14700133

    申请日：2015-04-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Ta-Chuan LIAO ,  Chien-Kuo YANG ,  Yi-Shao LIU ,  Tung-Tsun CHEN ,  Chan-Ching LIN ,  Jui-Cheng HUANG ,  Felix Ying-Kit TSUI ,  Jing-Hwang YANG

    IPC: G01N27/414

    CPC classification number: G01N27/4145

    Abstract: A biological device includes a substrate, a gate electrode, and a sensing well. The substrate includes a source region, a drain region, a channel region, a body region, and a sensing region. The channel region is disposed between the source region and the drain region. The sensing region is at least disposed between the channel region and the body region. The gate electrode is at least disposed on or above the channel region of the substrate. The sensing well is at least disposed adjacent to the sensing region.

    Abstract translation: 生物装置包括衬底，栅电极和感测阱。 衬底包括源极区，漏极区，沟道区，体区和感测区。 沟道区域设置在源极区域和漏极区域之间。 感测区域至少设置在通道区域和身体区域之间。 栅电极至少设置在衬底的沟道区上或上。 感测井至少设置在感测区域附近。

    MECHANISMS FOR PREVENTING LEAKAGE CURRENTS IN MEMORY CELLS
    4.
    发明申请
    MECHANISMS FOR PREVENTING LEAKAGE CURRENTS IN MEMORY CELLS 有权
    用于防止记忆细胞中的漏电流的机制

    公开(公告)号：US20150098266A1

    公开(公告)日：2015-04-09

    申请号：US14048873

    申请日：2013-10-08

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Shih-Hsien CHEN ,  Hau-Yan LU ,  Liang-Tai KUO ,  Chun-Yao KO ,  Felix Ying-Kit TSUI

    IPC: H01L27/108 ,  G11C11/401

    CPC classification number: G11C11/401 ,  G06F3/0625 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3418 ,  H01L27/11558

    Abstract: Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation.

    Abstract translation: 提供了存储单元及其操作方法。 存储器件包括多个存储器单元。 每个存储单元包括第一晶体管，开关和电容器。 第一晶体管具有连接到相应位线的漏极。 开关具有连接到第一晶体管的源极的第一端子和耦合到参考电压的第二端子。 电容器具有第一板和第二板，并且电容器的第一板电连接到第一晶体管的栅极。 电容器的第二板连接到相应的字线。 当存储单元未被选择执行写入操作或读取操作时，开关被关闭。

    TWO-DIMENSIONAL GRATING COUPLER AND METHODS OF MAKING SAME
    5.
    发明公开
    TWO-DIMENSIONAL GRATING COUPLER AND METHODS OF MAKING SAME 审中-公开

    公开(公告)号：US20230296846A1

    公开(公告)日：2023-09-21

    申请号：US18201110

    申请日：2023-05-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Tsung SHIH ,  Chewn-pu JOU ,  Stefan RUSU ,  Felix Ying-Kit TSUI ,  Lan-Chou CHO

    IPC: G02B6/34 ,  G02B6/30

    CPC classification number: G02B6/34 ,  G02B6/305

    Abstract: Disclosed are apparatus and methods for optical coupling. In one example, a method for forming an optical coupler, includes: forming an insulation layer on a semiconductor substrate; epitaxially growing a semiconductor material on the insulation layer to form a semiconductor layer; etching, according to a predetermined pattern, the semiconductor layer to form: an array of etched holes in the semiconductor layer to form a grating region, a first taper structure extending from a first side of the grating region, wherein a shape of the first taper structure in the semiconductor layer is a first triangle that is asymmetric about any line perpendicular to the first side of the grating region, and a second taper structure extending from a second side of the grating region, wherein a shape of the second taper structure in the semiconductor layer is a second triangle that is asymmetric about any line perpendicular to the second side of the grating region, wherein the first side and the second side are substantially perpendicular to each other; and depositing a dielectric material into the array of etched regions to form an array of scattering elements in the semiconductor layer, wherein the scattering elements are arranged to form a two-dimensional (2D) grating.

    SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF
    7.
    发明申请
    SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF 有权
    半导体结构及其制造方法

    公开(公告)号：US20150311140A1

    公开(公告)日：2015-10-29

    申请号：US14262582

    申请日：2014-04-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Alexander KALNITSKY ,  Hsiao-Chin TUAN ,  Shih-Fen HUANG ,  Hsin-Li CHENG ,  Felix Ying-Kit TSUI

    IPC: H01L23/48 ,  H01L21/265 ,  H01L21/22 ,  H01L21/768

    CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.

    Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括具有顶表面和底表面的晶片衬底，以及通过晶片衬底的顶表面和底表面由深沟槽绝缘体限定的晶片衬底中的导电柱。 制造半导体结构的方法包括以下步骤。 从晶片衬底的顶表面形成深沟槽以在晶片衬底中限定导电区域。 导电区域掺杂有掺杂剂。 深沟槽填充有绝缘材料以形成深沟槽绝缘体。 并且晶片衬底从晶片衬底的底表面变薄以暴露深沟槽绝缘体并隔离导电区域以形成导电柱。

    TWO-DIMENSIONAL GRATING COUPLER AND METHODS OF MAKING SAME
    8.
    发明公开
    TWO-DIMENSIONAL GRATING COUPLER AND METHODS OF MAKING SAME 审中-公开

    公开(公告)号：US20240361533A1

    公开(公告)日：2024-10-31

    申请号：US18769241

    申请日：2024-07-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Tsung SHIH ,  Chewn-Pu JOU ,  Stefan RUSU ,  Felix Ying-Kit TSUI ,  Lan-Chou CHO

    IPC: G02B6/34 ,  G02B6/30

    CPC classification number: G02B6/34 ,  G02B6/305

    Abstract: Disclosed are apparatus and methods for optical coupling. In one example, a method for forming an optical coupler, includes: forming an insulation layer on a semiconductor substrate; epitaxially growing a semiconductor material on the insulation layer to form a semiconductor layer; etching, according to a predetermined pattern, the semiconductor layer to form: an array of etched holes in the semiconductor layer to form a grating region, a first taper structure extending from a first side of the grating region, wherein a shape of the first taper structure in the semiconductor layer is a first triangle that is asymmetric about any line perpendicular to the first side of the grating region, and a second taper structure extending from a second side of the grating region, wherein a shape of the second taper structure in the semiconductor layer is a second triangle that is asymmetric about any line perpendicular to the second side of the grating region, wherein the first side and the second side are substantially perpendicular to each other; and depositing a dielectric material into the array of etched regions to form an array of scattering elements in the semiconductor layer, wherein the scattering elements are arranged to form a two-dimensional (2D) grating.

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