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    Layout modification method and system
    4.
    发明授权
    Layout modification method and system 有权
    布局修改方法和系统

    公开(公告)号：US09400866B2

    公开(公告)日：2016-07-26

    申请号：US14833260

    申请日：2015-08-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Xiang Lee ,  Li-Chung Hsu ,  Shih-Hsien Yang ,  Ho Che Yu ,  King-Ho Tam ,  Chung-Hsing Wang

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/02 ,  G06F2217/78 ,  G06F2217/84

    Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identities a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

    Abstract translation: 一种方法包括提供一种非暂时的机器可读存储介质，其存储至少部分先前采集的集成电路（IC）布局的部分网表，其表示用于制造具有IC布局的IC的一组光掩模， 该IC满足第一规格值。 计算机识别IC布局中的多个第一设备的正确子集，使得经修改的IC布局中的第二设备的第一设备的适当子集的替换满足与第一规范值不同的第二规范值。 至少一个布局掩模被生成并存储在至少一个非暂时机器可读存储介质中，可由用于形成至少一个附加光掩模的工具访问，使得该组光掩模和至少一个附加光掩模可用于制造 一个IC根据修订的IC布局。

    Switch cell structure and method
    6.
    发明授权
    Switch cell structure and method 有权

    公开(公告)号：US09900005B2

    公开(公告)日：2018-02-20

    申请号：US15167139

    申请日：2016-05-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chih-Liang Chen ,  Chi-Yeh Yu ,  Ho Che Yu

    IPC: H03K17/687

    CPC classification number: H03K17/6874 ,  H03K19/0005

    Abstract: A switch cell structure includes a switch cell of a first type, which includes a master switch cell and a plurality of slave switch cells. The master switch cell includes a buffer having an input and an output and a transistor having a gate coupled to the output of the buffer. The slave switch cell includes a respective signal line having an input and output and a transistor having a gate coupled to the signal line, the signal lines of the slave switch cells are coupled to one another, with the output of one coupled to the input of another of the signal lines. The output of the buffer of the master switch cell is coupled to an input of one of the signal lines of slave switch cells to drive the plurality of slave switch cells.

    Layout boundary method
    7.
    发明授权
    Layout boundary method 有权
    布局边界法

    公开(公告)号：US09262570B2

    公开(公告)日：2016-02-16

    申请号：US13919037

    申请日：2013-06-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Hsiung Hsu ,  Wen-Hao Chen ,  Ho Che Yu

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.

    Abstract translation: 本公开的一些实施例涉及实现与多图案化过程兼容的布局的方法和装置。 两个或多个单元电池被构造成具有满足多图案化工艺的性质的布局，并且分解成两种或更多种颜色以支持多图案化工艺。 活动布局特征与两个单位单元之间的共享边界处的虚拟线合并。 在共享边界处的两个活动布局特征之间短路的情况下，自动布局后方法可以重新排列共享边界附近的布局特征，以分离活动布局特征以实现单元功能，同时满足多图案化 属性。

    Layout modification method and system
    8.
    发明授权
    Layout modification method and system 有权
    布局修改方法和系统

    公开(公告)号：US09122839B2

    公开(公告)日：2015-09-01

    申请号：US14449211

    申请日：2014-08-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Meng-Xiang Lee ,  Li-Chung Hsu ,  Shih-Hsien Yang ,  Ho Che Yu ,  King-Ho Tam ,  Chung-Hsing Wang

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F2217/02 ,  G06F2217/78 ,  G06F2217/84

    Abstract: A method comprises providing a non-transitory, machine-readable storage medium storing a partial netlist of at least a portion of a previously taped-out integrated circuit (IC) layout, representing a set of photomasks for fabricating an IC having the IC layout such that the IC meets a first specification value. A computer identifies a proper subset of a plurality of first devices in the IC layout, such that replacement of the proper subset of the first devices by second devices in a revised IC layout satisfies a second specification value different from the first specification value. At least one layout mask is generated and stored in at least one non-transitory machine readable storage medium, accessible by a tool for forming at least one additional photomask, such that the set of photomasks and the at least one additional photomask are usable to fabricate an IC according to the revised IC layout.

    Abstract translation: 一种方法包括提供一种非暂时的机器可读存储介质，其存储至少部分先前采集的集成电路（IC）布局的部分网表，其表示用于制造具有IC布局的IC的一组光掩模， 该IC满足第一规格值。 计算机识别IC布局中的多个第一设备的正确子集，使得经修订的IC布局中的第二设备对第一设备的正确子集的替换满足与第一规范值不同的第二规范值。 至少一个布局掩模被生成并存储在至少一个非暂时机器可读存储介质中，可由用于形成至少一个附加光掩模的工具访问，使得该组光掩模和至少一个附加光掩模可用于制造 一个IC根据修订的IC布局。

    LAYOUT BOUNDARY METHOD
    9.
    发明申请
    LAYOUT BOUNDARY METHOD 有权
    布局边界方法

    公开(公告)号：US20140282344A1

    公开(公告)日：2014-09-18

    申请号：US13919037

    申请日：2013-06-17

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chin-Hsiung Hsu ,  Wen-Hao Chen ,  Ho Che Yu

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.

    Abstract translation: 本公开的一些实施例涉及实现与多图案化过程兼容的布局的方法和装置。 两个或多个单元电池被构造成具有满足多图案化工艺的性质的布局，并且分解成两种或更多种颜色以支持多图案化工艺。 活动布局特征与两个单位单元之间的共享边界处的虚拟线合并。 在共享边界处的两个活动布局特征之间短路的情况下，自动布局后方法可以重新排列共享边界附近的布局特征，以分离活动布局特征以实现单元功能，同时满足多图案化 属性。

    Switch Cell Structure and Method
    10.
    发明申请
    Switch Cell Structure and Method 有权

    公开(公告)号：US20170346485A1

    公开(公告)日：2017-11-30

    申请号：US15167139

    申请日：2016-05-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

    Inventor： Chih-Liang Chen ,  Chi-Yeh Yu ,  Ho Che Yu

    IPC: H03K17/687

    CPC classification number: H03K17/6874 ,  H03K19/0005

    Abstract: A switch cell structure includes a switch cell of a first type, which includes a master switch cell and a plurality of slave switch cells. The master switch cell includes a buffer having an input and an output and a transistor having a gate coupled to the output of the buffer. The slave switch cell includes a respective signal line having an input and output and a transistor having a gate coupled to the signal line, the signal lines of the slave switch cells are coupled to one another, with the output of one coupled to the input of another of the signal lines. The output of the buffer of the master switch cell is coupled to an input of one of the signal lines of slave switch cells to drive the plurality of slave switch cells.

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