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公开(公告)号：US10529711B2
公开(公告)日：2020-01-07
申请号：US15684442
申请日：2017-08-23
发明人： Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang , Fu-Huan Tsai , Hsieh-Hung Hsieh , Tzu-Jin Yeh , Han-Min Tsai , Hong-Lin Chu
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/167 , H01L29/10 , H01L29/423 , H01L29/417 , H03D7/14 , H01L21/8238
摘要： A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.
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公开(公告)号：US11094694B2
公开(公告)日：2021-08-17
申请号：US16732194
申请日：2019-12-31
发明人： Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang , Fu-Huan Tsai , Hsieh-Hung Hsieh , Tzu-Jin Yeh , Han-Min Tsai , Hong-Lin Chu
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/167 , H01L29/10 , H01L29/423 , H01L29/417 , H03D7/14 , H01L29/66 , H01L29/78 , H01L21/8238
摘要： A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.
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公开(公告)号：US20170352660A1
公开(公告)日：2017-12-07
申请号：US15684442
申请日：2017-08-23
发明人： Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang , Fu-Huan Tsai , Hsieh-Hung Hsieh , Tzu-Jin Yeh , Han-Min Tsai , Hong-Lin Chu
IPC分类号： H01L27/088 , H01L29/423 , H01L21/8234 , H01L29/10 , H01L29/167 , H03D7/14 , H01L29/417 , H01L21/8238
CPC分类号： H01L27/0886 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/1033 , H01L29/167 , H01L29/41783 , H01L29/42376 , H01L29/66795 , H01L29/785 , H03D7/1441 , H03D7/1458
摘要： A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.
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公开(公告)号：US09929760B2
公开(公告)日：2018-03-27
申请号：US15098784
申请日：2016-04-14
发明人： Hong-Lin Chu , Hsieh-Hung Hsieh , Tzu-Jin Yeh
CPC分类号： H04B1/1036 , H03F1/565 , H03F3/193 , H03F3/3022 , H03F3/45071 , H03F2200/165 , H03F2200/171 , H03F2200/213 , H03F2200/222 , H03F2200/294 , H03F2200/336 , H03F2200/451 , H03F2203/30031 , H03F2203/45288 , H03H19/004
摘要： A tunable matching circuit for use with ultra-low power RF receivers is described to support a variety of RF communication bands. A switched-capacitor array and a switched-resistor array are used to adjust the input impedance presented by the operating characteristics of transistors in an ultra-low-power mode. An RF sensor may be used to monitor performance of the tunable matching circuit and thereby determine optimal setting of the digital control word that drives the switched-capacitor array and switched-resistor array. An effective match over a significant bandwidth is achievable. The optimal matching configuration may be updated at any time to adjust to changing operating conditions. Memory may be used to store the optimal matching configurations of the switched capacitor array and switched resistor array.
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公开(公告)号：US09761584B2
公开(公告)日：2017-09-12
申请号：US14732661
申请日：2015-06-05
发明人： Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang , Fu-Huan Tsai , Hsieh-Hung Hsieh , Tzu-Jin Yeh , Han-Min Tsai , Hong-Lin Chu
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/167 , H01L29/10 , H01L29/423 , H01L29/417 , H03D7/14
CPC分类号： H01L27/0886 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/1033 , H01L29/167 , H01L29/41783 , H01L29/42376 , H03D7/1441 , H03D7/1458
摘要： A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.
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公开(公告)号：US11063559B2
公开(公告)日：2021-07-13
申请号：US14732670
申请日：2015-06-05
发明人： Chia-Chung Chen , Chi-Feng Huang , Victor Chiang Liang , Fu-Huan Tsai , Hsieh-Hung Hsieh , Tzu-Jin Yeh , Han-Min Tsai , Hong-Lin Chu
IPC分类号： H03D7/14 , H01L29/167 , H01L21/8234 , H01L29/10 , H01L29/66 , H01L29/78 , H01L21/8238
摘要： A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.
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公开(公告)号：US10256783B2
公开(公告)日：2019-04-09
申请号：US15714395
申请日：2017-09-25
发明人： Hong-Lin Chu , Hsieh-Hung Hsieh , Tzu-Jin Yeh
摘要： A transmission frontend includes a modulator configured to generate a modulated signal. A first selectable path is electrically coupled to the modulator and is configured to generate a first signal having a first power level. A second selectable path is electrically coupled to the modulator and is configured to generate a second signal having a second power level. The first power level is greater than the second power level. A transformer is electrically coupled to each of the first selectable path and the second selectable path. An antenna is electrically coupled to the transformer.
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