公开(公告)号：US20230361039A1

公开(公告)日：2023-11-09

申请号：US18351957

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/8234 ,  H01L29/06 ,  H01L23/528 ,  H01L21/768 ,  H01L29/786 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/786

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ru

公开(公告)号：US20220293528A1

公开(公告)日：2022-09-15

申请号：US17242783

申请日：2021-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US11742290B2

公开(公告)日：2023-08-29

申请号：US17242783

申请日：2021-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/786 ,  H01L29/7851

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US20240413087A1

公开(公告)日：2024-12-12

申请号：US18790012

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US12165975B2

公开(公告)日：2024-12-10

申请号：US18351957

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.