公开(公告)号：US20220293528A1

公开(公告)日：2022-09-15

申请号：US17242783

申请日：2021-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US11810827B2

公开(公告)日：2023-11-07

申请号：US17338929

申请日：2021-06-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/823821 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/7843 ,  H01L29/7846 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/823892 ,  H01L27/0928

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

公开(公告)号：US11742290B2

公开(公告)日：2023-08-29

申请号：US17242783

申请日：2021-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/786 ,  H01L29/7851

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US11031299B2

公开(公告)日：2021-06-08

申请号：US16045992

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

公开(公告)号：US11264505B2

公开(公告)日：2022-03-01

申请号：US17027078

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Yen-Chun Lin

IPC: H01L29/78 ,  H01L21/22 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L23/532 ,  H01L29/423 ,  H01L21/768 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/324

Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.

公开(公告)号：US20240413087A1

公开(公告)日：2024-12-12

申请号：US18790012

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US12165975B2

公开(公告)日：2024-12-10

申请号：US18351957

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US20210013337A1

公开(公告)日：2021-01-14

申请号：US17027078

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ling Chan ,  Yen-Chun Lin

IPC: H01L29/78 ,  H01L21/22 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L23/532 ,  H01L29/423 ,  H01L21/768 ,  H01L21/308 ,  H01L21/8238 ,  H01L21/324

Abstract: A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.

公开(公告)号：US10522417B2

公开(公告)日：2019-12-31

申请号：US15725544

申请日：2017-10-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.

公开(公告)号：US20180350697A1

公开(公告)日：2018-12-06

申请号：US16045992

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Lung Cheng ,  Yen-Chun Lin ,  Da-Wen Lin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/7843

Abstract: A semiconductor device includes a P-type Field Effect Transistor (PFET) and an NFET. The PFET includes an N-well disposed in a substrate, a first fin structure disposed over the N-well, a first liner layer disposed over the N-well, and a second liner layer disposed over the first liner layer. The first liner layer and the second liner layer include different materials. The NFET includes a P-well disposed in the substrate, a second fin structure disposed over the P-well, a third liner layer disposed over the P-well. The third liner layer and the second liner layer include the same materials.