公开(公告)号：US10475877B1

公开(公告)日：2019-11-12

申请号：US16106525

申请日：2018-08-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Chung Hsu ,  Chung-Long Chang ,  Tsung-Yu Yang ,  Hung-Chi Li ,  Cheng-Chieh Hsieh ,  Che-Yung Lin ,  Grace Chang

IPC分类号： H01L49/02 ,  H01L23/00 ,  H01F27/28 ,  H01F27/24 ,  H01F27/29 ,  H05K1/18 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/321 ,  H01L21/027

摘要： A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

公开(公告)号：US20200286981A1

公开(公告)日：2020-09-10

申请号：US16879913

申请日：2020-05-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Chung Hsu ,  Chung-Long Chang ,  Tsung-Yu Yang ,  Hung-Chi Li ,  Cheng-Chieh Hsieh ,  Che-Yung Lin ,  Grace Chang

IPC分类号： H01L49/02 ,  H01L23/00 ,  H01F27/28 ,  H01F27/24 ,  H01F27/29 ,  H05K1/18 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522

摘要： A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

公开(公告)号：US20200066831A1

公开(公告)日：2020-02-27

申请号：US16587305

申请日：2019-09-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Chung Hsu ,  Chung-Long Chang ,  Tsung-Yu Yang ,  Hung-Chi Li ,  Cheng-Chieh Hsieh ,  Che-Yung Lin ,  Grace Chang

IPC分类号： H01L49/02 ,  H01L23/522 ,  H01F27/28 ,  H01L23/00 ,  H01F27/29 ,  H01F27/24 ,  H01L21/768 ,  H05K1/18 ,  H01L23/528

摘要： A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.

公开(公告)号：US20230144244A1

公开(公告)日：2023-05-11

申请号：US18153532

申请日：2023-01-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Chang Ku ,  Hung-Chi Li ,  Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wensen Hung

IPC分类号： H01L23/427 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/427 ,  H01L21/4882 ,  H01L25/50 ,  H01L25/0655

摘要： A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

公开(公告)号：US20210233833A1

公开(公告)日：2021-07-29

申请号：US17228018

申请日：2021-04-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Chang Ku ,  Hung-Chi Li ,  Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wensen Hung

IPC分类号： H01L23/427 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

摘要： A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

公开(公告)号：US20210098333A1

公开(公告)日：2021-04-01

申请号：US16737832

申请日：2020-01-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Chang Ku ,  Wensen Hung ,  Hung-Chi Li

IPC分类号： H01L23/40 ,  H01L23/473 ,  H01L23/00

摘要： A package structure including a reconstructed wafer, a heat dissipation substrate, a semiconductor device, and a fixing mechanism is provided. The heat dissipation substrate is disposed on a side of the reconstructed wafer and includes an inlet, a base plate located between the inlet and the reconstructed wafer, and a connection member located and coupled between the inlet and the base plate. The connection member has an inclined fluid channel that descends from the inlet to the base plate. The semiconductor device is disposed on another side of the reconstructed wafer, wherein the heat dissipation substrate and the semiconductor device are respectively located on opposite sides of the reconstructed wafer. The fixing mechanism fixes the reconstructed wafer, the heat dissipation substrate, and the semiconductor device together.

公开(公告)号：US11594469B2

公开(公告)日：2023-02-28

申请号：US17228018

申请日：2021-04-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Chang Ku ,  Hung-Chi Li ,  Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wensen Hung

IPC分类号： H01L23/34 ,  H01L23/427 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

摘要： A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

公开(公告)号：US11282766B2

公开(公告)日：2022-03-22

申请号：US16737832

申请日：2020-01-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Chang Ku ,  Wensen Hung ,  Hung-Chi Li

IPC分类号： H01L23/40 ,  H01L23/473 ,  H01L23/00

摘要： A package structure including a reconstructed wafer, a heat dissipation substrate, a semiconductor device, and a fixing mechanism is provided. The heat dissipation substrate is disposed on a side of the reconstructed wafer and includes an inlet, a base plate located between the inlet and the reconstructed wafer, and a connection member located and coupled between the inlet and the base plate. The connection member has an inclined fluid channel that descends from the inlet to the base plate. The semiconductor device is disposed on another side of the reconstructed wafer, wherein the heat dissipation substrate and the semiconductor device are respectively located on opposite sides of the reconstructed wafer. The fixing mechanism fixes the reconstructed wafer, the heat dissipation substrate, and the semiconductor device together.

公开(公告)号：US20210280491A1

公开(公告)日：2021-09-09

申请号：US17328266

申请日：2021-05-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsung-Shu Lin ,  Wensen Hung ,  Hung-Chi Li ,  Tsung-Yu Chen

IPC分类号： H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

摘要： In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.

公开(公告)号：US10672860B2

公开(公告)日：2020-06-02

申请号：US16587305

申请日：2019-09-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ching-Chung Hsu ,  Chung-Long Chang ,  Tsung-Yu Yang ,  Hung-Chi Li ,  Cheng-Chieh Hsieh ,  Che-Yung Lin ,  Grace Chang

IPC分类号： H01L49/02 ,  H01F27/28 ,  H01L23/00 ,  H01F27/29 ,  H01F27/24 ,  H01L21/768 ,  H05K1/18 ,  H01L23/528 ,  H01L23/522 ,  H01L21/321 ,  H01L21/027

摘要： A multi-terminal inductor and method for forming the multi-terminal inductor are provided. In some embodiments, an interconnect structure is arranged over a semiconductor substrate. A passivation layer is arranged over the interconnect structure. A first magnetic layer is arranged over the passivation layer, and a conductive wire laterally extends from a first input/output (I/O) bond structure at a first location to a second I/O bond structure at a second location. A third I/O bond structure branches off of the conductive wire at a third location between the first location and the second location. A connection between the third I/O bond structure and the first I/O bond structure has a first inductance. Alternatively, a connection between the first I/O bond structure and the second I/O bond structure has a second inductance different than the first inductance.