公开(公告)号：US20240088093A1

公开(公告)日：2024-03-14

申请号：US18149793

申请日：2023-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wensen Hung ,  Tsung-Yu Chen ,  Wen-Hsin Wei ,  Hsien-Pin Hu

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/473 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/473 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/08112 ,  H01L2224/16227 ,  H01L2924/10161 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1461 ,  H01L2924/16251 ,  H01L2924/1631 ,  H01L2924/1811 ,  H01L2924/182

Abstract: In an embodiment, a method includes: attaching a package component to a package substrate, the package component includes: a first die being disposed over an interposer; a second die being disposed over the interposer and laterally adjacent to the first die; and an encapsulant being disposed around the first die and the second die; attaching a thermal interface material to the first die and the second die; and attaching a lid structure to the package substrate, the lid structure includes: a lid cap being disposed over the thermal interface material; and a plurality of lid feet connecting the lid cap to the package substrate, in a plan view the plurality of lid feet forming a discontinuous loop around the package component.

公开(公告)号：US11810833B2

公开(公告)日：2023-11-07

申请号：US17373250

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wensen Hung ,  Tsung-Yu Chen ,  Tsung-Shu Lin ,  Chen-Hsiang Lao ,  Wen-Hsin Wei ,  Hsien-Pin Hu

IPC: H01L23/48 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L21/67 ,  H01L23/40

CPC classification number: H01L23/3675 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/4878 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/67092 ,  H01L23/3185 ,  H01L23/40 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16225

Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.

公开(公告)号：US20210193550A1

公开(公告)日：2021-06-24

申请号：US16718211

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wensen Hung ,  Ping-Kang Huang ,  Sao-Ling Chiu ,  Tsung-Shu Lin ,  Tsung-Yu Chen ,  Chien-Yuan Huang ,  Chen-Hsiang Lao

IPC: H01L23/367 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a metallic cover. The semiconductor package is disposed on the circuit substrate. The metallic cover is disposed over the semiconductor package and over the circuit substrate. The metallic cover comprises a lid and outer flanges. The lid overlies the semiconductor package. The outer flanges are disposed at edges of the lid, are connected with the lid, extend from the lid towards the circuit substrate, and face side surfaces of the semiconductor package. The lid has a first region that is located over the semiconductor package and is thicker than a second region that is located outside a footprint of the semiconductor package.

公开(公告)号：US20240222218A1

公开(公告)日：2024-07-04

申请号：US18604957

申请日：2024-03-14

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Wensen Hung ,  Szu-Po Huang ,  Hsiang-Fan Lee ,  Kim Hong Chen ,  Chi-Hsi Wu ,  Shin-Puu Jeng

IPC: H01L23/36 ,  H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367 ,  H01L23/42 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/36 ,  H01L23/04 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33519 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/1679 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

公开(公告)号：US11961779B2

公开(公告)日：2024-04-16

申请号：US17331945

申请日：2021-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wensen Hung ,  Szu-Po Huang ,  Hsiang-Fan Lee ,  Kim Hong Chen ,  Chi-Hsi Wu ,  Shin-Puu Jeng

IPC: H01L23/36 ,  H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367 ,  H01L23/42 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/36 ,  H01L23/04 ,  H01L23/10 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/49822 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/33519 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/1679 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/291 ,  H01L2924/014

Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.

公开(公告)号：US11594469B2

公开(公告)日：2023-02-28

申请号：US17228018

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chang Ku ,  Hung-Chi Li ,  Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wensen Hung

IPC: H01L23/34 ,  H01L23/427 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

公开(公告)号：US11282825B2

公开(公告)日：2022-03-22

申请号：US16877504

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wensen Hung

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/40 ,  H01L23/46

Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.

公开(公告)号：US11282766B2

公开(公告)日：2022-03-22

申请号：US16737832

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chang Ku ,  Wensen Hung ,  Hung-Chi Li

IPC: H01L23/40 ,  H01L23/473 ,  H01L23/00

Abstract: A package structure including a reconstructed wafer, a heat dissipation substrate, a semiconductor device, and a fixing mechanism is provided. The heat dissipation substrate is disposed on a side of the reconstructed wafer and includes an inlet, a base plate located between the inlet and the reconstructed wafer, and a connection member located and coupled between the inlet and the base plate. The connection member has an inclined fluid channel that descends from the inlet to the base plate. The semiconductor device is disposed on another side of the reconstructed wafer, wherein the heat dissipation substrate and the semiconductor device are respectively located on opposite sides of the reconstructed wafer. The fixing mechanism fixes the reconstructed wafer, the heat dissipation substrate, and the semiconductor device together.

公开(公告)号：US20210366889A1

公开(公告)日：2021-11-25

申请号：US16877504

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Shu Lin ,  Tsung-Yu Chen ,  Wensen Hung

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/46 ,  H01L23/40

Abstract: A structure including a wiring substrate, an interposer disposed on and electrically connected to the wiring substrate, a semiconductor die disposed on and electrically connected to the interposer, a first insulating encapsulation disposed on the interposer, a second insulating encapsulation disposed on the wiring substrate, and a lid is provided. The semiconductor die is laterally encapsulated by the first insulating encapsulation. The semiconductor die and the first insulating encapsulation are laterally encapsulated by the second insulating encapsulation. A top surface of the first insulating encapsulation is substantially leveled with a top surface of the second insulating encapsulation and a surface of the semiconductor die. The lid is disposed on the semiconductor die, the first insulating encapsulation and the second insulating encapsulation.

公开(公告)号：US20210280491A1

公开(公告)日：2021-09-09

申请号：US17328266

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Shu Lin ,  Wensen Hung ,  Hung-Chi Li ,  Tsung-Yu Chen

IPC: H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

Abstract: In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.