公开(公告)号：US20210202713A1

公开(公告)日：2021-07-01

申请号：US17181607

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hua Pan ,  Je-Wei Hsu ,  Hua Feng Chen ,  Jyun-Ming Lin ,  Chen-Huang Peng ,  Min-Yann Hsieh ,  Java Wu

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/311 ,  H01L29/78 ,  H01L29/45 ,  H01L21/768 ,  H01L29/417 ,  H01L23/485

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

公开(公告)号：US20240072155A1

公开(公告)日：2024-02-29

申请号：US18504745

申请日：2023-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hua Pan ,  Je-Wei Hsu ,  Hua Feng Chen ,  Jyun-Ming Lin ,  Chen-Huang Peng ,  Min-Yann Hsieh ,  Java Wu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/768 ,  H01L23/485 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/31144 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/28518

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

公开(公告)号：US11862708B2

公开(公告)日：2024-01-02

申请号：US17181607

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hua Pan ,  Je-Wei Hsu ,  Hua Feng Chen ,  Jyun-Ming Lin ,  Chen-Huang Peng ,  Min-Yann Hsieh ,  Java Wu

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L23/485 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L29/665 ,  H01L21/31144 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/28518

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.