公开(公告)号：US20240072155A1

公开(公告)日：2024-02-29

申请号：US18504745

申请日：2023-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hua Pan ,  Je-Wei Hsu ,  Hua Feng Chen ,  Jyun-Ming Lin ,  Chen-Huang Peng ,  Min-Yann Hsieh ,  Java Wu

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/768 ,  H01L23/485 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/31144 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/28518

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

公开(公告)号：US11862708B2

公开(公告)日：2024-01-02

申请号：US17181607

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hua Pan ,  Je-Wei Hsu ,  Hua Feng Chen ,  Jyun-Ming Lin ,  Chen-Huang Peng ,  Min-Yann Hsieh ,  Java Wu

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L23/485 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L29/665 ,  H01L21/31144 ,  H01L21/76831 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L21/28518

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

公开(公告)号：US10522412B2

公开(公告)日：2019-12-31

申请号：US15898919

申请日：2018-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Shuo Ho ,  Tsung-Yu Chiang ,  Chia-Ming Chang ,  Jyun-Ming Lin

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L21/283 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/51

Abstract: Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.

公开(公告)号：US09899265B2

公开(公告)日：2018-02-20

申请号：US15383837

申请日：2016-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Shuo Ho ,  Tsung-Yu Chiang ,  Chia-Ming Chang ,  Jyun-Ming Lin

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L21/283 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/51

CPC classification number: H01L21/823456 ,  H01L21/0273 ,  H01L21/28008 ,  H01L21/28123 ,  H01L21/283 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659

Abstract: Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.

公开(公告)号：US20210202713A1

公开(公告)日：2021-07-01

申请号：US17181607

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Hua Pan ,  Je-Wei Hsu ,  Hua Feng Chen ,  Jyun-Ming Lin ,  Chen-Huang Peng ,  Min-Yann Hsieh ,  Java Wu

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/311 ,  H01L29/78 ,  H01L29/45 ,  H01L21/768 ,  H01L29/417 ,  H01L23/485

Abstract: A method includes forming a transistor, which includes forming a dummy gate stack over a semiconductor region, and forming an Inter-Layer Dielectric (ILD). The dummy gate stack is in the ILD, and the ILD covers a source/drain region in the semiconductor region. The method further includes removing the dummy gate stack to form a trench in the first ILD, forming a low-k gate spacer in the trench, forming a replacement gate dielectric extending into the trench, forming a metal layer to fill the trench, and performing a planarization to remove excess portions of the replacement gate dielectric and the metal layer to form a gate dielectric and a metal gate, respectively. A source region and a drain region are then formed on opposite sides of the metal gate.

公开(公告)号：US09882023B2

公开(公告)日：2018-01-30

申请号：US15056454

申请日：2016-02-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyun-Ming Lin ,  Hua Feng Chen ,  Kuo-Hua Pan ,  Min-Yann Hsieh ,  C. H. Wu

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L29/423 ,  H01L29/51 ,  H01L23/535

CPC classification number: H01L29/66553 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/823431 ,  H01L21/823468 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/4238 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78

Abstract: A semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first gate electrode of a transistor, a first sidewall spacer along a sidewall of the gate pattern, a first insulating layer in contact with the first sidewall spacer and having a planarized top surface, and a second sidewall spacer formed on the planarized top surface of the first insulating layer. The second sidewall spacer may be formed over the first sidewall spacer. A width of the second sidewall spacer is equal to or greater than a width of the first sidewall spacer.

公开(公告)号：US09524965B2

公开(公告)日：2016-12-20

申请号：US14178906

申请日：2014-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Shuo Ho ,  Tsung-Yu Chiang ,  Chia-Ming Chang ,  Jyun-Ming Lin

IPC: H01L21/283 ,  H01L27/088 ,  H01L27/092 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768 ,  H01L29/51

CPC classification number: H01L21/823456 ,  H01L21/0273 ,  H01L21/28008 ,  H01L21/28123 ,  H01L21/283 ,  H01L21/31051 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659

Abstract: Embodiments of a semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a substrate and a first metal gate structure formed over the substrate. The first metal gate structure has a first width. The semiconductor device structure further includes a first contact formed adjacent to the first metal gate structure and a second metal gate structure formed over the substrate. The second metal gate structure has a second width smaller than the first width. The semiconductor device structure further includes an insulating layer formed over the second metal gate structure and a second contact self-aligned to the second metal gate structure.

Abstract translation: 提供半导体器件结构的实施例及其形成方法。 半导体器件结构包括衬底和形成在衬底上的第一金属栅极结构。 第一金属栅极结构具有第一宽度。 半导体器件结构还包括邻近第一金属栅极结构形成的第一触点和形成在衬底上的第二金属栅极结构。 第二金属栅极结构具有小于第一宽度的第二宽度。 半导体器件结构还包括形成在第二金属栅极结构上的绝缘层和与第二金属栅极结构自对准的第二接触。