公开(公告)号：US20230253256A1

公开(公告)日：2023-08-10

申请号：US18303173

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Shan-Mei Liao ,  Jer-Fu Wang ,  Yung-Hsiang Chan

IPC: H01L21/8234 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28

CPC classification number: H01L21/823462 ,  H01L29/517 ,  H01L27/0886 ,  H01L21/28185

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

公开(公告)号：US20210257258A1

公开(公告)日：2021-08-19

申请号：US16939610

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Shan-Mei Liao ,  Jer-Fu Wang ,  Yung-Hsiang Chan

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/51

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

公开(公告)号：US20240387277A1

公开(公告)日：2024-11-21

申请号：US18783597

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Shan-Mei Liao ,  Jer-Fu Wang ,  Yung-Hsiang Chan

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/51

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

公开(公告)号：US20240412991A1

公开(公告)日：2024-12-12

申请号：US18491237

申请日：2023-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-En Lee ,  MingYuan Song ,  Hung-Li Chiang ,  Jer-Fu Wang ,  Chao-Ching Cheng ,  Iuliana Radu

IPC: H01L21/67 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes forming first bonding pads over a first substrate, wherein the first bonding pads include a layer of ferromagnetic material, wherein each first bonding pad produces a respective magnetic field having a first orientation; and bonding second bonding pads to the first bonding pads using metal-to-metal bonding.

公开(公告)号：US11664279B2

公开(公告)日：2023-05-30

申请号：US16939610

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Shan-Mei Liao ,  Jer-Fu Wang ,  Yung-Hsiang Chan

IPC: H01L21/8234 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28

CPC classification number: H01L21/823462 ,  H01L21/28185 ,  H01L27/0886 ,  H01L29/517

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.