公开(公告)号：US20240387277A1

公开(公告)日：2024-11-21

申请号：US18783597

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Shan-Mei Liao ,  Jer-Fu Wang ,  Yung-Hsiang Chan

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/51

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

公开(公告)号：US20170250280A1

公开(公告)日：2017-08-31

申请号：US15054086

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Yung-Yu Wang ,  Yung-Hsiang Chan ,  Chia-Ying Tsai ,  Ting-Chun Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least one gate structure is disposed over the substrate and on the isolation structures. The spacers are disposed on sidewalls of the at least one gate structure. First blocking material layers are disposed on the spacers. The strained source and drain regions are disposed at two opposite sides of the at least one gate structure. Second blocking material layers are disposed on the strained source and drain regions. The first and second blocking material layers comprise oxygen-rich oxide materials.

公开(公告)号：US20230253256A1

公开(公告)日：2023-08-10

申请号：US18303173

申请日：2023-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Shan-Mei Liao ,  Jer-Fu Wang ,  Yung-Hsiang Chan

IPC: H01L21/8234 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28

CPC classification number: H01L21/823462 ,  H01L29/517 ,  H01L27/0886 ,  H01L21/28185

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

公开(公告)号：US20210257258A1

公开(公告)日：2021-08-19

申请号：US16939610

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Shan-Mei Liao ,  Jer-Fu Wang ,  Yung-Hsiang Chan

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/51

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

公开(公告)号：US11664279B2

公开(公告)日：2023-05-30

申请号：US16939610

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hung Huang ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Shan-Mei Liao ,  Jer-Fu Wang ,  Yung-Hsiang Chan

IPC: H01L21/8234 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28

CPC classification number: H01L21/823462 ,  H01L21/28185 ,  H01L27/0886 ,  H01L29/517

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

公开(公告)号：US10026838B2

公开(公告)日：2018-07-17

申请号：US15054086

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Yung-Yu Wang ,  Yung-Hsiang Chan ,  Chia-Ying Tsai ,  Ting-Chun Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least one gate structure is disposed over the substrate and on the isolation structures. The spacers are disposed on sidewalls of the at least one gate structure. First blocking material layers are disposed on the spacers. The strained source and drain regions are disposed at two opposite sides of the at least one gate structure. Second blocking material layers are disposed on the strained source and drain regions. The first and second blocking material layers comprise oxygen-rich oxide materials.