公开(公告)号：US09984967B2

公开(公告)日：2018-05-29

申请号：US15065770

申请日：2016-03-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Yu Cheng ,  Shih-Kang Tien ,  Ching-Kun Huang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.

公开(公告)号：US09799741B2

公开(公告)日：2017-10-24

申请号：US15053499

申请日：2016-02-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kai-Yu Cheng

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L23/31 ,  H01L29/49

CPC classification number: H01L29/41791 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/3171 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts.

公开(公告)号：US11508849B2

公开(公告)日：2022-11-22

申请号：US16915500

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Kai-Yu Cheng ,  Chih-Han Lin ,  Sin-Yi Yang ,  Horng-Huei Tseng

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.

公开(公告)号：US20200328308A1

公开(公告)日：2020-10-15

申请号：US16915500

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Kai-Yu Cheng ,  Chih-Han Lin ,  Sin-Yi Yang ,  Horng-Huei Tseng

IPC: H01L29/78 ,  H01L29/417 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.