公开(公告)号：US11791338B2

公开(公告)日：2023-10-17

申请号：US17585020

申请日：2022-01-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Chih-Hsiung Huang ,  Chung-En Tsai ,  Chee-Wee Liu ,  Kun-Wa Kuok ,  Yi-Hsiu Hsiao

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/40

CPC classification number: H01L27/092 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

公开(公告)号：US11961768B2

公开(公告)日：2024-04-16

申请号：US18312647

申请日：2023-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Wen Chiu ,  Da-Yuan Lee ,  Hsien-Ming Lee ,  Kai-Cyuan Yang ,  Yu-Sheng Wang ,  Chih-Hsiang Fan ,  Kun-Wa Kuok

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

公开(公告)号：US20230274983A1

公开(公告)日：2023-08-31

申请号：US18312647

申请日：2023-05-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Wen Chiu ,  Da-Yuan Lee ,  Hsien-Ming Lee ,  Kai-Cyuan Yang ,  Yu-Sheng Wang ,  Chih-Hsiang Fan ,  Kun-Wa Kuok

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/513

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

公开(公告)号：US12249604B2

公开(公告)日：2025-03-11

申请号：US18360416

申请日：2023-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Chih-Hsiung Huang ,  Chung-En Tsai ,  Chee-Wee Liu ,  Kun-Wa Kuok ,  Yi-Hsiu Hsiao

IPC: H01L29/40 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a gate stack, and epitaxy structures. The substrate has a P-type region. The gate stack is over the P-type region of the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. Dipoles are formed between the top WF metal layer and the bottom WF metal layer, and the dipoles direct from the bottom WF metal layer to the top WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structures are over the P-type region of the substrate and on opposite sides of the gate stack.

公开(公告)号：US20210043521A1

公开(公告)日：2021-02-11

申请号：US17068041

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Wen Chiu ,  Da-Yuan Lee ,  Hsien-Ming Lee ,  Kai-Cyuan Yang ,  Yu-Sheng Wang ,  Chih-Hsiang Fan ,  Kun-Wa Kuok

IPC: H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/51

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

公开(公告)号：US11682589B2

公开(公告)日：2023-06-20

申请号：US17068041

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Wen Chiu ,  Da-Yuan Lee ,  Hsien-Ming Lee ,  Kai-Cyuan Yang ,  Yu-Sheng Wang ,  Chih-Hsiang Fan ,  Kun-Wa Kuok

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L21/823821 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517

Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

公开(公告)号：US11244945B2

公开(公告)日：2022-02-08

申请号：US16548730

申请日：2019-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Chih-Hsiung Huang ,  Chung-En Tsai ,  Chee-Wee Liu ,  Kun-Wa Kuok ,  Yi-Hsiu Hsiao

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/40

Abstract: A semiconductor device includes a substrate, a gate stack, and an epitaxy structure. The gate stack over the substrate and includes a gate dielectric layer, a bottom work function (WF) metal layer, a top WF metal layer, and a filling metal. The bottom WF metal layer is over the gate dielectric layer. The top WF metal layer is over and in contact with the bottom WF metal layer. At least one of the top and bottom WF metal layers includes dopants, and the top WF metal layer is thicker than the bottom WF metal layer. The filling metal is over the top WF metal layer. The epitaxy structure is over the substrate and adjacent the gate stack.