公开(公告)号：US11239255B1

公开(公告)日：2022-02-01

申请号：US17071845

申请日：2020-10-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED ,  TSMC CHINA COMPANY LIMITED

Inventor： Tian-Yu Xie ,  Xin-Yong Wang ,  Lei Pan ,  Kuo-Ji Chen

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78

Abstract: An IC structure includes first and second transistors, an isolation region and a first gate extension. The first transistor includes a first gate and first source/drain regions respectively on opposite sides of the first gate. The second transistor includes a second gate and second source/drain regions respectively on opposite sides of the second gate. The isolation region is laterally between the first and second transistors. A first one of the first source/drain regions has a first source/drain extension protruding from a first boundary of the isolation region, and a first one of the second source/drain regions has a second source/drain extension protruding from a second boundary of the isolation region. The first gate extension extends from the first gate to a position overlapping the isolation region.

公开(公告)号：US12191301B2

公开(公告)日：2025-01-07

申请号：US17853698

申请日：2022-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC CHINA COMPANY LIMITED

Inventor： Ya-Qi Ma ,  Lei Pan ,  Zhen Tang

IPC: H01L27/02 ,  H01L27/06

Abstract: An integrated circuit includes first to second transistors and a resistive device. The first transistor is coupled between a pad and a first voltage terminal that provides a first supply voltage. The second transistor is coupled in parallel with the first transistor. A breakdown voltage of the first transistor is different from a trigger voltage of the second transistor. The resistive device is coupled between the pad and a second voltage terminal that provides a second supply voltage higher than the first supply voltage, and operates with the second supply voltage in an electrostatic discharge (ESD) event when the first and second transistors discharge a ESD current between the pad and the first voltage terminal.

公开(公告)号：US11380671B2

公开(公告)日：2022-07-05

申请号：US16807003

申请日：2020-03-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC CHINA COMPANY LIMITED

Inventor： Ya-Qi Ma ,  Lei Pan ,  Zhen Tang

IPC: H01L27/02 ,  H01L27/06

Abstract: An integrated circuit includes a pull-up circuit, an electrostatic discharge (ESD) primary circuit, and a pull-down circuit. The pull-up circuit is coupled between a pad and a first voltage terminal. The ESD primary circuit includes a first terminal which is coupled to the pad and the pull-up circuit, and a second terminal coupled to a second voltage terminal different from the first voltage terminal. The pull-down circuit has a first terminal which is coupled to the pad, the ESD primary circuit and the pull-up circuit, and a second terminal coupled to the second voltage terminal. The pull-down circuit includes at least one first transistor of a first conductivity type having a first terminal coupled to the first terminal of the pull-down circuit. A breakdown voltage of the at least one first transistor is greater than a trigger voltage of the ESD primary circuit.

公开(公告)号：US09048655B2

公开(公告)日：2015-06-02

申请号：US13675547

申请日：2012-11-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Qingchao Meng ,  Lei Pan ,  Shao-Yu Chou

IPC: H02H9/00 ,  H02H9/04 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06

CPC classification number: H02H9/043 ,  H02H9/046

Abstract: Some embodiments relate to an IC that includes an ESD-susceptible circuit. The IC includes a number of IC pads that are electrically coupled to respective nodes on the ESD-susceptible circuit. The IC pads are electrically accessible from external to the IC, and include one or more power supply pads and one or more I/O pads. The IC also includes a number of ESD protection devices coupled to the plurality of IC pads, respectively. A trigger circuit on the IC is configured to detect an ESD event impingent on a power supply pad and, in response to the detection, to trigger concurrent shunting of energy of the ESD event over both an ESD clamp element of an I/O pad and an ESD clamp element of the power supply pad. Other embodiments are also disclosed.

Abstract translation: 一些实施例涉及包括ESD敏感电路的IC。 IC包括多个IC焊盘，其电耦合到ESD敏感电路上的相应节点。 IC焊盘可以从IC的外部电可访问，并且包括一个或多个电源焊盘和一个或多个I / O焊盘。 IC还包括分别耦合到多个IC焊盘的多个ESD保护器件。 IC上的触发电路被配置为检测照射在电源焊盘上的ESD事件，并且响应于该检测，触发I / O焊盘的ESD钳位元件上ESD事件的能量并发分流，以及 电源板的ESD钳位元件。 还公开了其他实施例。

公开(公告)号：US10291230B2

公开(公告)日：2019-05-14

申请号：US15700033

申请日：2017-09-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lei Pan

IPC: H03L5/00 ,  H03K19/177 ,  H03K19/017 ,  H03K19/0185 ,  H02M3/07 ,  H03K3/356 ,  H03K3/0233

Abstract: A level shifter includes a level switching circuit, an input circuit, and a first voltage drop circuit. The level switching circuit is configured to adjust a first voltage level of a first node and a second voltage level of a second node in response to a first input signal and a second input signal. The input circuit is configured to receive the first input signal and the second input signal. The first voltage drop circuit is coupled between the level switching circuit and the input circuit, and is configured to track a voltage level of a third node which is coupled to the first node, in order to be turned on according to the voltage level of the third node.

公开(公告)号：US20140118869A1

公开(公告)日：2014-05-01

申请号：US13675547

申请日：2012-11-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Qingchao Meng ,  Lei Pan ,  Shao-Yu Chou

IPC: H02H9/04

CPC classification number: H02H9/043 ,  H02H9/046

Abstract: Some embodiments relate to an IC that includes an ESD-susceptible circuit. The IC includes a number of IC pads that are electrically coupled to respective nodes on the ESD-susceptible circuit. The IC pads are electrically accessible from external to the IC, and include one or more power supply pads and one or more I/O pads. The IC also includes a number of ESD protection devices coupled to the plurality of IC pads, respectively. A trigger circuit on the IC is configured to detect an ESD event impingent on a power supply pad and, in response to the detection, to trigger concurrent shunting of energy of the ESD event over both an ESD clamp element of an I/O pad and an ESD clamp element of the power supply pad. Other embodiments are also disclosed.

Abstract translation: 一些实施例涉及包括ESD敏感电路的IC。 IC包括多个IC焊盘，其电耦合到ESD敏感电路上的相应节点。 IC焊盘可以从IC的外部电可访问，并且包括一个或多个电源焊盘和一个或多个I / O焊盘。 IC还包括分别耦合到多个IC焊盘的多个ESD保护器件。 IC上的触发电路被配置为检测照射在电源焊盘上的ESD事件，并且响应于该检测，触发I / O焊盘的ESD钳位元件上ESD事件的能量并发分流，以及 电源板的ESD钳位元件。 还公开了其他实施例。

公开(公告)号：US11769772B2

公开(公告)日：2023-09-26

申请号：US17586285

申请日：2022-01-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  TSMC NANJING COMPANY LIMITED ,  TSMC CHINA COMPANY LIMITED

Inventor： Tian-Yu Xie ,  Xin-Yong Wang ,  Lei Pan ,  Kuo-Ji Chen

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/78

Abstract: An IC structure includes first and second gates, first and second source/drain regions, and an isolation region. The first and second gates each have a first portion extending along a first direction and a second portion extending along a second direction. The first source/drain regions are respectively on opposite sides of the first portion of the first gate. The second source/drain regions are respectively on opposite sides of the first portion of the second gate. The isolation region has a lower portion between a first one of the first source/drain regions and a first one of the second source/drain regions, and an upper portion partially overlapping with the second portion of first gate and the second portion of the second gate. A width of the lower portion is a less than a width of the upper portion.