公开(公告)号：US20250087639A1

公开(公告)日：2025-03-13

申请号：US18401846

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ke-Gang Wen ,  Yu-Bey Wu ,  Tsung-Chieh Hsiao ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

Abstract: A method includes forming first integrated circuits on a front side of a semiconductor substrate of a first device die, forming a trench capacitor extending from a backside of the semiconductor substrate into the semiconductor substrate, and forming a first through-via and a second through-via penetrating through the semiconductor substrate. The trench capacitor is electrically coupled between the first through-via and the second through-via. A second device die is bonded to the first die. The second device die includes second integrated circuits, and power nodes of the second integrated circuits are electrically coupled to the first through-via and the second through-via.

公开(公告)号：US20210359095A1

公开(公告)日：2021-11-18

申请号：US17301431

申请日：2021-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Yu-Fan Peng ,  Li-Ting Chen ,  Yu-Shan Lu ,  Yu-Bey Wu ,  Wei-Chung Sun ,  Yuan-Ching Peng ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Pei-Yi Liu ,  Jing Yi Yan

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/786 ,  H01L29/40

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

公开(公告)号：US10157843B2

公开(公告)日：2018-12-18

申请号：US15816843

申请日：2017-11-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey Wu ,  Dian-Hau Chen ,  Jye-Yen Cheng ,  Sheng-Hsuan Wei ,  Li-Yu Lee ,  TaiYang Wu

IPC: H01L21/76 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

公开(公告)号：US20250149427A1

公开(公告)日：2025-05-08

申请号：US18434222

申请日：2024-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yueh Chou ,  Hsiang-Ku Shen ,  Chen-Chiu Huang ,  Yu-Bey Wu ,  Dian-Hau Chen

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: In an embodiment, a device includes: a plurality of redistribution lines over a semiconductor substrate, the redistribution lines including trace portions extending along the semiconductor substrate; a first passivation layer over the redistribution lines, the first passivation layer filling an entirety of an area between the trace portions of the redistribution lines; a passive device over the first passivation layer; a dielectric layer over the passive device; and a die connector extending through the dielectric layer, the die connector physically and electrically coupled to the passive device.

公开(公告)号：US09852992B2

公开(公告)日：2017-12-26

申请号：US15484344

申请日：2017-04-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey Wu ,  Dian-Hau Chen ,  Jye-Yen Cheng ,  Sheng-Hsuan Wei ,  Li-Yu Lee ,  TaiYang Wu

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/033

CPC classification number: H01L23/5329 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

公开(公告)号：US20250149482A1

公开(公告)日：2025-05-08

申请号：US18587104

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shan Hsieh ,  Chen-Chiu Huang ,  Yu-Bey Wu ,  Hsiang-Ku Shen ,  Dian-Hau Chen

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: In an embodiment, a method includes forming active devices over a semiconductor substrate; forming an interconnect structure over the semiconductor substrate, the interconnect structure comprising a contact pad embedded in a dielectric layer; forming a first passivation layer over the interconnect structure; forming a first opening through the first passivation layer to expose the contact pad; depositing a seed layer over the first passivation layer and in the first opening; forming a sacrificial material over the seed layer; patterning the sacrificial material to reform the first opening and to form a second opening; depositing conductive material to form a first redistribution line in the first opening and a second redistribution line in the second opening; removing the sacrificial material; and attaching an integrated circuit die to the first redistribution line and the second redistribution line.

公开(公告)号：US12166096B2

公开(公告)日：2024-12-10

申请号：US18301554

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Yu-Fan Peng ,  Li-Ting Chen ,  Yu-Shan Lu ,  Yu-Bey Wu ,  Wei-Chung Sun ,  Yuan-Ching Peng ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Pei-Yi Liu ,  Jing Yi Yan

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

公开(公告)号：US20230253470A1

公开(公告)日：2023-08-10

申请号：US18301554

申请日：2023-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Yu-Fan Peng ,  Li-Ting Chen ,  Yu-Shan Lu ,  Yu-Bey Wu ,  Wei-Chung Sun ,  Yuan-Ching Peng ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Pei-Yi Liu ,  Jing Yi Yan

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42376 ,  H01L21/82385 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/401 ,  H01L29/0665 ,  H01L29/785 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/78642

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

公开(公告)号：US11355436B2

公开(公告)日：2022-06-07

申请号：US17135791

申请日：2020-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Bey Wu ,  Dian-Hau Chen ,  Jye-Yen Cheng ,  Sheng-Hsuan Wei ,  Li-Yu Lee ,  TaiYang Wu

IPC: H01L21/76 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, first recesses are formed in the first dielectric layer. Metal wirings extending is a first direction are formed in the first recesses. A mask layer is formed over the metal wirings and the first dielectric layer, which includes a first opening extending in the first direction and is located above a space between adjacent two metal wirings. A first groove corresponding to the first opening is formed between the adjacent two metal wirings by etching the first dielectric layer using the mask layer as an etching mask. A second dielectric layer is formed so that a first air gap is formed in the first groove. A width of the first opening in a perpendicular direction to the first direction is smaller than a space between the adjacent two metal wirings.

公开(公告)号：US20250070064A1

公开(公告)日：2025-02-27

申请号：US18403064

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ke-Gang Wen ,  Yu-Bey Wu ,  Liang-Wei Wang ,  Hsin-Feng Chen ,  Tsung-Chieh Hsiao ,  Chih Chuan Su ,  Dian-Hau Chen

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.