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    Interconnect formation and structure
    1.
    发明授权
    Interconnect formation and structure 有权

    公开(公告)号：US10804140B2

    公开(公告)日：2020-10-13

    申请号：US15939572

    申请日：2018-03-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Pin-Wen Chen ,  Chia-Han Lai ,  Mei-Hui Fu ,  Min-Hsiu Hung ,  Ya-Yi Cheng

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/762

    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.

    Conductive feature structure including a blocking region
    2.
    发明授权
    Conductive feature structure including a blocking region 有权

    公开(公告)号：US11532503B2

    公开(公告)日：2022-12-20

    申请号：US17101858

    申请日：2020-11-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Pin-Wen Chen ,  Chia-Han Lai ,  Mei-Hui Fu ,  Min-Hsiu Hung ,  Ya-Yi Cheng

    IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/762

    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.

    Conductive Feature Formation and Structure
    3.
    发明申请
    Conductive Feature Formation and Structure 有权

    公开(公告)号：US20210074580A1

    公开(公告)日：2021-03-11

    申请号：US17101858

    申请日：2020-11-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Pin-Wen Chen ,  Chia-Han Lai ,  Mei-Hui Fu ,  Min-Hsiu Hung ,  Ya-Yi Cheng

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.

    Conductive Feature Formation and Structure
    5.
    发明申请
    Conductive Feature Formation and Structure 审中-公开

    公开(公告)号：US20190385904A1

    公开(公告)日：2019-12-19

    申请号：US16556383

    申请日：2019-08-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Pin-Wen Chen ,  Chia-Han Lai ,  Mei-Hui Fu ,  Min-Hsiu Hung ,  Ya-Yi Cheng

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.

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