公开(公告)号：US20220367667A1

公开(公告)日：2022-11-17

申请号：US17869521

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen Cheng ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Hong-Mao Lee ,  Ming-Hsing Tsai ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yan-Ming Tsai ,  Yu-Shiuan Wang ,  Hung-Hsu Chen ,  Wei-Yip Loh ,  Ya-Yi Cheng

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/326 ,  H01L29/78 ,  H01L29/08

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

公开(公告)号：US10804140B2

公开(公告)日：2020-10-13

申请号：US15939572

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chia-Han Lai ,  Mei-Hui Fu ,  Min-Hsiu Hung ,  Ya-Yi Cheng

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/762

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.

公开(公告)号：US20200152763A1

公开(公告)日：2020-05-14

申请号：US16740881

申请日：2020-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wen Cheng ,  Cheng-Tung Lin ,  Chih-Wei Chang ,  Hong-Mao Lee ,  Ming-Hsing Tsai ,  Sheng-Hsuan Lin ,  Wei-Jung Lin ,  Yan-Ming Tsai ,  Yu-Shiuan Wang ,  Hung-Hsu Chen ,  Wei-Yip Loh ,  Ya-Yi Cheng

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/78 ,  H01L21/02 ,  H01L21/326 ,  H01L29/45

Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.

公开(公告)号：US20240387265A1

公开(公告)日：2024-11-21

申请号：US18786535

申请日：2024-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chang-Ting Chung ,  Yi-Hsiang Chao ,  Yu-Ting Wen ,  Kai-Chieh Yang ,  Yu-Chen Ko ,  Peng-Hao Hsu ,  Ya-Yi Cheng ,  Min-Hsiu Hung ,  Chun-Hsien Huang ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/535

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

公开(公告)号：US20230260836A1

公开(公告)日：2023-08-17

申请号：US17663315

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei Shan Chang ,  Yi-Hsiang Chao ,  Chun-Hsien Huang ,  Peng-Hao Hsu ,  Kevin Lee ,  Shu-Lan Chang ,  Ya-Yi Cheng ,  Ching-Yi Chen ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai

IPC: H01L21/768 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/76852 ,  H01L29/78618 ,  H01L29/0665 ,  H01L29/78696 ,  H01L29/66742 ,  H01L21/823418 ,  H01L21/76876

Abstract: A method includes forming a dielectric layer over a source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source/drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.

公开(公告)号：US11532503B2

公开(公告)日：2022-12-20

申请号：US17101858

申请日：2020-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chia-Han Lai ,  Mei-Hui Fu ,  Min-Hsiu Hung ,  Ya-Yi Cheng

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/762

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.

公开(公告)号：US20210074580A1

公开(公告)日：2021-03-11

申请号：US17101858

申请日：2020-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chia-Han Lai ,  Mei-Hui Fu ,  Min-Hsiu Hung ,  Ya-Yi Cheng

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.

公开(公告)号：US10475702B2

公开(公告)日：2019-11-12

申请号：US15920727

申请日：2018-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chia-Han Lai ,  Chih-Wei Chang ,  Mei-Hui Fu ,  Ming-Hsing Tsai ,  Wei-Jung Lin ,  Yu Shih Wang ,  Ya-Yi Cheng ,  I-Li Chen

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/3213 ,  H01L21/285

Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

公开(公告)号：US20240379433A1

公开(公告)日：2024-11-14

申请号：US18782900

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Chia-Han Lai ,  Chih-Wei Chang ,  Mei-Hui Fu ,  Ming-Hsing Tsai ,  Wei-Jung Lin ,  Yu-Shih Wang ,  Ya-Yi Cheng ,  I-Li Chen

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/3213 ,  H01L23/535

Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

公开(公告)号：US20240363353A1

公开(公告)日：2024-10-31

申请号：US18449443

申请日：2023-08-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pin-Wen Chen ,  Yu-Chen Ko ,  Chi-Yuan Chen ,  Ya-Yi Cheng ,  Chun-I Tsai ,  Wei-Jung Lin ,  Chih-Wei Chang ,  Ming-Hsing Tsai ,  Syun-Ming Jang ,  Wei-Jen Lo

IPC: H01L21/285 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/28518 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source/drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source/drain region around the gate structure; forming an opening in the ILD layer to expose the source/drain region; forming a silicide region and a barrier layer successively in the openings over the source/drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.