公开(公告)号：US20200211962A1

公开(公告)日：2020-07-02

申请号：US16380502

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao TSAI ,  Techi WONG ,  Meng-Liang LIN ,  Yi-Wen WU ,  Po-Yao CHUANG ,  Shin-Puu JENG

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: A package structure and method for forming the same are provided. The package structure includes a die structure formed over a first interconnect structure, and the die structure includes a first region and a second region. The package structure includes a dam structure formed on the first region of the die structure, and a second interconnect structure formed over the die structure and the dam structure. The package structure also includes a package layer formed between the first interconnect structure and the second interconnect structure, and the package layer is formed on the second region of the die structure to surround the dam structure.

公开(公告)号：US20180350765A1

公开(公告)日：2018-12-06

申请号：US15609523

申请日：2017-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hua CHANG ,  Jing-Cheng LIN ,  Po-Hao TSAI

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure, and a first conductive layer on the first transition layer. The first conductive layer is substantially made of twinned copper.

公开(公告)号：US20180151540A1

公开(公告)日：2018-05-31

申请号：US15362690

申请日：2016-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua YU ,  Jing-Cheng LIN ,  Po-Hao TSAI ,  An-Jhih SU

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L23/60

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L23/60 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film is electrically connected to the first ground bump.

公开(公告)号：US20200211956A1

公开(公告)日：2020-07-02

申请号：US16406600

申请日：2019-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Wen WU ,  Techi WONG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Shih-Ting HUNG ,  Shin-Puu JENG

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die formed over an interconnect structure, an encapsulating layer formed over the interconnect structure to cover and surround the semiconductor die, and an interposer structure formed over the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure includes island layers arranged on the first surface of the insulating base and corresponding to the semiconductor die. A portion of the encapsulating layer is sandwiched by at least two of the island layers. Alternatively, the interposer structure includes a passivation layer covering the second surface of the insulating base and having a recess that is extended along a peripheral edge of the insulating base.

公开(公告)号：US20200075350A1

公开(公告)日：2020-03-05

申请号：US16242311

申请日：2019-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao TSAI ,  Shih-Ting HUNG ,  Shin-Puu JENG ,  Techi WONG

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/18

Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive structure over a substrate. The substrate includes a dielectric layer and a wiring layer in the dielectric layer, and the conductive structure is electrically connected to the wiring layer. The method includes forming a first molding layer over the substrate and surrounding the conductive structure. The method includes forming a redistribution structure over the first molding layer and the conductive structure. The method includes bonding a chip structure to the redistribution structure.

公开(公告)号：US20210125961A1

公开(公告)日：2021-04-29

申请号：US16918188

申请日：2020-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hao TSAI ,  Ming-Da CHENG ,  Mirng-Ji LII

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/42 ,  H01L21/52 ,  H01L21/56 ,  H01L25/00

Abstract: A package structure is provided. The package structure includes a substrate having a first surface and a second surface opposite the first surface. The substrate includes a cavity extending from the second surface toward the first surface, and thermal vias extending from a bottom surface of the cavity to the first surface. The package structure also includes at least one electronic device formed in the cavity and thermally coupled to the thermal vias. In addition, the package structure includes an insulating layer formed over the second surface and covering the first electronic device. The insulating layer includes a redistribution layer (RDL) structure electrically connected to the electronic device. The package structure also includes an encapsulating material formed in the cavity, extending along sidewalls of the electronic device and between the electronic device and the insulating layer.

公开(公告)号：US20200098693A1

公开(公告)日：2020-03-26

申请号：US16180511

申请日：2018-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shin-Puu JENG ,  Techi WONG ,  Po-Yao LIN ,  Ming-Chih YEW ,  Po-Hao TSAI ,  Po-Yao CHUANG

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L21/683 ,  H01L25/10 ,  H01L23/31

Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive pillar over a redistribution structure. The method includes bonding a chip to the redistribution structure. The method includes forming a molding layer over the redistribution structure. The molding layer surrounds the conductive pillar and the chip, and the conductive pillar passes through the molding layer. The method includes forming a cap layer over the molding layer and the conductive pillar. The cap layer has a through hole exposing the conductive pillar, and the cap layer includes fibers. The method includes forming a conductive via structure in the through hole. The conductive via structure is connected to the conductive pillar.

公开(公告)号：US20200075503A1

公开(公告)日：2020-03-05

申请号：US16284630

申请日：2019-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yao CHUANG ,  Po-Hao TSAI ,  Shin-Puu JENG ,  Shuo-Mao CHEN ,  Ming-Chih YEW

IPC: H01L23/552 ,  H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive structures surround the semiconductor die. The method further includes forming a protective layer to surround the conductive structures and the semiconductor die. In addition, the method includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.

公开(公告)号：US20250087648A1

公开(公告)日：2025-03-13

申请号：US18958990

申请日：2024-11-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng LIN ,  Po-Hao TSAI

IPC: H01L25/11 ,  H01L21/02 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/427 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: A package structure includes a first semiconductor package and a second semiconductor package over the first semiconductor package. The first semiconductor package includes a dielectric structure, a semiconductor device on the dielectric structure, under bump metallization (UBM) structures in the dielectric structure. The USB structures each include a first region and a second region surrounded by the first region. The first region has more metal layers than the second region. The bumps are respectively on the second regions of the UBM structures.

公开(公告)号：US20220059515A1

公开(公告)日：2022-02-24

申请号：US17516458

申请日：2021-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jing-Cheng LIN ,  Po-Hao TSAI

IPC: H01L25/11 ,  H01L25/00 ,  H01L25/10 ,  H01L21/683 ,  H01L21/02 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.