公开(公告)号：US20180315728A1

公开(公告)日：2018-11-01

申请号：US15499962

申请日：2017-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan PEI ,  Chih-Chiang TSAO ,  Wei-Yu CHEN ,  Hsiu-Jen LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56

CPC classification number: H01L24/19 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/25 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68368 ,  H01L2224/13024 ,  H01L2224/19 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2224/73209 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/3511

Abstract: Structures and formation methods of a chip package are provided. The method includes forming a protective layer to surround a semiconductor die, and the protective layer has opposing first and second surfaces. The method also includes forming a dielectric layer over the first surface of the protective layer and the semiconductor die. The method further includes forming a conductive feature over the dielectric layer such that the conductive feature is electrically connected to a conductive element of the semiconductor die. In addition, the method includes printing a warpage-control element over the second surface of the protective layer and the semiconductor die such that the semiconductor die is between the warpage-control element and the dielectric layer.

公开(公告)号：US20170317038A1

公开(公告)日：2017-11-02

申请号：US15227060

申请日：2016-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Peng TSAI ,  Sheng-Feng WENG ,  Sheng-Hsiang CHIU ,  Meng-Tse CHEN ,  Chih-Wei LIN ,  Wei-Hung LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/60 ,  H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H05K9/00 ,  H01L25/065

CPC classification number: H01L23/60 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K9/0073 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a first shielding feature over a base layer. The package structure also includes a package layer encapsulating the integrated circuit die and the first shielding feature. The package structure further includes a second shielding feature extending from the side surface of the base layer towards the first shielding feature to electrically connect to the first shielding feature. The side surface of the second shielding feature faces away from the side surface of the base layer and is substantially coplanar with the side surface of the package layer.

公开(公告)号：US20170316957A1

公开(公告)日：2017-11-02

申请号：US15195321

申请日：2016-06-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shing-Chao CHEN ,  Chih-Wei LIN ,  Meng-Tse CHEN ,  Hui-Min HUANG ,  Ming-Da CHENG ,  Kuo-Lung PAN ,  Wei-Sen CHANG ,  Tin-Hao KUO ,  Hao-Yi TSAI

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/48 ,  H01L23/58

CPC classification number: H01L21/566 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/585 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/81

Abstract: Structures and formation methods of a chip package are provided. The method includes forming multiple conductive structures over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes disposing a mold over the carrier substrate. The method further includes forming a protection layer between the mold and the carrier substrate to surround the semiconductor die and the conductive structures. In addition, the method includes removing the mold.

公开(公告)号：US20210375748A1

公开(公告)日：2021-12-02

申请号：US17197483

申请日：2021-03-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Ming HUANG ,  Ming-Da CHENG ,  Songbor LEE ,  Jung-You CHEN ,  Ching-Hua KUAN ,  Tzy-Kuang LEE

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/00

Abstract: A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.

公开(公告)号：US20210134746A1

公开(公告)日：2021-05-06

申请号：US17019173

申请日：2020-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ching-Yu CHANG ,  Ming-Da CHENG ,  Ming-Hui WENG

IPC: H01L23/00 ,  C08G73/10

Abstract: A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.

公开(公告)号：US20200294944A1

公开(公告)日：2020-09-17

申请号：US16888758

申请日：2020-05-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan TAI ,  Ting-Ting KUO ,  Yu-Chih HUANG ,  Chih-Wei LIN ,  Hsiu-Jen LIN ,  Chih-Hua CHEN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Hao-Yi TSAI ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/683

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

公开(公告)号：US20180286823A1

公开(公告)日：2018-10-04

申请号：US15726260

申请日：2017-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan TAI ,  Ting-Ting KUO ,  Yu-Chih HUANG ,  Chih-Wei LIN ,  Hsiu-Jen LIN ,  Chih-Hua CHEN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Hao-Yi TSAI ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L23/31

Abstract: A method of forming a package structure includes disposing a semiconductor device over a first dielectric layer, wherein a first redistribution line is in the first dielectric layer, forming a molding compound over the first dielectric layer and in contact with a sidewall of the semiconductor device, forming a second dielectric layer over the molding compound and the semiconductor device, forming a first opening in the second dielectric layer, the molding compound, and the first dielectric layer to expose the first redistribution line, and forming a first conductor in the first opening, wherein the first conductor is electrically connected to the first redistribution line.

公开(公告)号：US20170287890A1

公开(公告)日：2017-10-05

申请号：US15628745

申请日：2017-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： James HU ,  Ming-Da CHENG ,  Chung-Shi LIU

IPC: H01L25/00 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L25/105 ,  H01L2224/11 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/0001

Abstract: A semiconductor device package is provided. The semiconductor device package includes a first substrate and a conductive element fared on the first substrate. The conductive element has a recess away from the first substrate, and the recess has a first depth greater than a second depth from a top surface of the conductive element to a center of the conductive element semiconductor device package includes a conductive connector bonded to the conductive element, and a melting point of the conductive element is higher than a melting point of the conductive connector, and the conductive connector is filled into the recess of the conductive element.

公开(公告)号：US20240290734A1

公开(公告)日：2024-08-29

申请号：US18655596

申请日：2024-05-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan TAI ,  Ting-Ting KUO ,  Yu-Chih HUANG ,  Chih-Wei LIN ,  Hsiu-Jen LIN ,  Chih-Hua CHEN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Hao-Yi TSAI ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L24/02 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L23/3128 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/02311 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/12105

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

公开(公告)号：US20220165689A1

公开(公告)日：2022-05-26

申请号：US17670481

申请日：2022-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hsuan TAI ,  Ting-Ting KUO ,  Yu-Chih HUANG ,  Chih-Wei LIN ,  Hsiu-Jen LIN ,  Chih-Hua CHEN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Hao-Yi TSAI ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/683

Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.