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公开(公告)号:US20200266051A1
公开(公告)日:2020-08-20
申请号:US16866131
申请日:2020-05-04
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jing-Cheng LIN
IPC: H01L21/02 , H01L21/822 , H01L27/06
Abstract: A method is disclosed that includes operations as follows: after forming an ion-implanted layer disposed between an epitaxial layer and a first semiconductor substrate, bounding the epitaxial layer to a bonding oxide layer without forming any layer between the epitaxial layer and the bonding oxide layer; and removing the first semiconductor substrate together with a portion of the ion-implanted layer and keeping a remaining portion of the ion-implanted layer on the epitaxial layer.
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公开(公告)号:US20180145011A1
公开(公告)日:2018-05-24
申请号:US15801935
申请日:2017-11-02
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jing-Cheng LIN
IPC: H01L23/48 , H01L21/768 , H01L23/00 , H01L25/065 , H01L25/00 , H01L27/06 , H01L21/762
CPC classification number: H01L23/481 , H01L21/76224 , H01L21/76898 , H01L24/80 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05563 , H01L2224/05564 , H01L2224/05572 , H01L2224/05573 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/08147 , H01L2224/13 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/80013 , H01L2224/80075 , H01L2224/80091 , H01L2224/80095 , H01L2224/80896 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06524 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/10333 , H01L2924/10335 , H01L2924/10338 , H01L2924/10342 , H01L2224/80 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
Abstract: Methods for forming a semiconductor device structure are provided. The method includes bonding a first wafer and a second wafer, and a first transistor is formed in a front-side of the first semiconductor wafer. The method further includes thinning a front-side of the second wafer and forming a second transistor in the front-side of the second wafer.
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公开(公告)号:US20160204084A1
公开(公告)日:2016-07-14
申请号:US15076141
申请日:2016-03-21
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jing-Cheng LIN
IPC: H01L25/065 , H01L25/00
CPC classification number: H01L23/481 , H01L21/76224 , H01L21/76898 , H01L24/80 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/05025 , H01L2224/05124 , H01L2224/05147 , H01L2224/05563 , H01L2224/05564 , H01L2224/05572 , H01L2224/05573 , H01L2224/05582 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/08147 , H01L2224/13 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/80013 , H01L2224/80075 , H01L2224/80091 , H01L2224/80095 , H01L2224/80896 , H01L2224/9202 , H01L2224/9212 , H01L2224/94 , H01L2225/06524 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/10333 , H01L2924/10335 , H01L2924/10338 , H01L2924/10342 , H01L2224/80 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
Abstract: Methods for forming a semiconductor device structure are provided. The method includes providing a first semiconductor wafer and a second semiconductor wafer. A first transistor is formed in a front-side of the first semiconductor wafer, and no devices are formed in the second semiconductor wafer. The method further includes bonding the front-side of the first semiconductor wafer to a backside of the second semiconductor wafer and thinning a front-side of the second semiconductor wafer. After thinning the second semiconductor wafer, a second transistor is formed in the front-side of the second semiconductor wafer. At least one first through substrate via (TSV) is formed in the second semiconductor wafer, and the first TSV directly contacts a conductive feature of the first semiconductor wafer.
Abstract translation: 提供了形成半导体器件结构的方法。 该方法包括提供第一半导体晶片和第二半导体晶片。 第一晶体管形成在第一半导体晶片的前侧,并且在第二半导体晶片中不形成器件。 该方法还包括将第一半导体晶片的正面接合到第二半导体晶片的背面并使第二半导体晶片的前侧变薄。 在使第二半导体晶片变薄之后,在第二半导体晶片的正面形成第二晶体管。 在第二半导体晶片中形成至少一个第一贯穿衬底通孔(TSV),并且第一TSV直接接触第一半导体晶片的导电特征。
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公开(公告)号:US20220277954A1
公开(公告)日:2022-09-01
申请号:US17745182
申请日:2022-05-16
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jing-Cheng LIN
IPC: H01L21/02 , H01L27/06 , H01L21/822
Abstract: A method is provided that includes operations as follows: bonding an epitaxial layer formed with a first semiconductor substrate and an ion-implanted layer that is formed between the epitaxial layer and the first semiconductor substrate, to a bonding oxide layer of a second semiconductor substrate; separating the first semiconductor substrate from the epitaxial layer, by removing the first semiconductor substrate together with a portion of the ion-implanted layer and keeping the epitaxial layer; and forming a first semiconductor device portion on the epitaxial layer, and an interconnect layer on the first semiconductor device portion.
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公开(公告)号:US20180350765A1
公开(公告)日:2018-12-06
申请号:US15609523
申请日:2017-05-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jung-Hua CHANG , Jing-Cheng LIN , Po-Hao TSAI
Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a chip structure. The semiconductor package structure includes a first conductive structure over the chip structure. The first conductive structure is electrically connected to the chip structure. The first conductive structure includes a first transition layer over the chip structure, and a first conductive layer on the first transition layer. The first conductive layer is substantially made of twinned copper.
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公开(公告)号:US20180286846A1
公开(公告)日:2018-10-04
申请号:US15997156
申请日:2018-06-04
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jing-Cheng LIN
IPC: H01L25/00 , H01L23/48 , H01L21/768 , H01L23/00 , H01L25/065
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a bonding structure formed between a first substrate and a second substrate. The bonding structure includes a first polymer bonded to a second polymer, and a first conductive material bonded to a second conductive material. The semiconductor device includes a first TSV formed in the first substrate and an interconnect structure formed over the first TSV. The first TSV is between the interconnect structure and the bonding structure.
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公开(公告)号:US20180151540A1
公开(公告)日:2018-05-31
申请号:US15362690
申请日:2016-11-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chen-Hua YU , Jing-Cheng LIN , Po-Hao TSAI , An-Jhih SU
IPC: H01L25/065 , H01L23/498 , H01L23/31 , H01L23/00 , H01L21/78 , H01L23/60
CPC classification number: H01L25/0657 , H01L21/561 , H01L21/568 , H01L21/78 , H01L23/3128 , H01L23/49822 , H01L23/49827 , H01L23/562 , H01L23/60 , H01L2224/18 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06548 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film is electrically connected to the first ground bump.
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公开(公告)号:US20150021789A1
公开(公告)日:2015-01-22
申请号:US14488017
申请日:2014-09-16
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jing-Cheng LIN
IPC: H01L23/00 , H01L21/768 , H01L23/48
CPC classification number: H01L24/82 , H01L21/76897 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/80 , H01L27/0688 , H01L2224/05547 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/08147 , H01L2224/80203 , H01L2224/80357 , H01L2224/80855 , H01L2224/80895 , H01L2224/80905 , H01L2224/9202 , H01L2924/00012 , H01L2924/00014
Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first semiconductor wafer and a second semiconductor wafer bonded via a hybrid bonding structure, and the hybrid bonding structure includes a first conductive material embedded in a polymer material and a second conductive material embedded in a second polymer material. The first conductive material of the first semiconductor wafer bonded to the second conductive material of the second semiconductor wafer and the first polymer material of the first semiconductor wafer is bonded to the second polymer material of the second semiconductor wafer. The semiconductor device structure further includes at least one through substrate via (TSV) extending from a bottom surface of the second semiconductor wafer to a top surface of the first semiconductor wafer.
Abstract translation: 提供了一种半导体器件结构及其形成方法。 半导体器件结构包括通过混合键合结构接合的第一半导体晶片和第二半导体晶片,并且该混合键合结构包括嵌入聚合物材料中的第一导电材料和嵌入第二聚合物材料中的第二导电材料。 与第二半导体晶片的第二导电材料接合的第一半导体晶片的第一导电材料和第一半导体晶片的第一聚合物材料接合到第二半导体晶片的第二聚合物材料。 半导体器件结构还包括从第二半导体晶片的底表面延伸到第一半导体晶片的顶表面的至少一个贯穿衬底通孔(TSV)。
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公开(公告)号:US20240014192A1
公开(公告)日:2024-01-11
申请号:US18474168
申请日:2023-09-25
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Jing-Cheng LIN , Po-Hao TSAI
IPC: H01L25/11 , H01L25/00 , H01L25/10 , H01L21/683 , H01L21/02 , H01L21/768 , H01L23/498 , H01L23/00 , H01L25/065
CPC classification number: H01L25/117 , H01L25/50 , H01L25/105 , H01L21/6835 , H01L21/02354 , H01L21/76883 , H01L23/49822 , H01L23/49838 , H01L24/03 , H01L24/09 , H01L24/11 , H01L24/14 , H01L25/0657 , H01L23/562 , H01L2224/32013 , H01L2224/1308 , H01L2224/83005 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/81 , H01L24/83 , H01L2221/68359 , H01L2224/05647 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/16227 , H01L2224/2919 , H01L2224/32225 , H01L2224/48227 , H01L2224/49113 , H01L2224/73204 , H01L2224/81005 , H01L2224/83102 , H01L2224/97 , H01L2924/18161 , H01L22/14
Abstract: A package structure includes a first semiconductor package and a second semiconductor package over the first semiconductor package. The first semiconductor package includes a dielectric structure, a semiconductor device on the dielectric structure, under bump metallization (UBM) structures in the dielectric structure. The USB structures each include a first region and a second region surrounded by the first region. The first region has more metal layers than the second region. The bumps are respectively on the second regions of the UBM structures.
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公开(公告)号:US20190115306A1
公开(公告)日:2019-04-18
申请号:US16229021
申请日:2018-12-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Jing-Cheng LIN , Po-Hao TSAI
IPC: H01L23/552 , H01L21/56 , H01L23/498 , H01L21/48 , H01L23/00 , H01L25/065
Abstract: Methods for forming chip package structures are provided. The method includes disposing a first chip structure, a second chip structure over a carrier substrate and forming a molding compound layer surrounding the first chip structure and the second chip structure. The method includes forming a dielectric structure over the molding compound layer and a first grounding line in the dielectric structure and cutting the first grounding line to form a first end enlarged portion of the first grounding line. In addition, the first end enlarged portion has a gradually increased thickness.
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