公开(公告)号：US09082496B2

公开(公告)日：2015-07-14

申请号：US13761545

申请日：2013-02-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： PoHao Lee ,  Chung-Cheng Chou

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1677 ,  G11C11/1693 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0066 ,  G11C2213/79

Abstract: A bit line, which is coupled to a resistive element of a memory cell is set to a first voltage level. The memory cell may be an MRAM cell or an RRAM cell. The resistive element is configured to have a first resistance in a first state of the memory cell and a second resistance in a second state of the memory cell. A source line, which is selectively coupled to the memory cell by an access transistor, is set to a second voltage level. A word line signal is asserted to apply a first bias voltage across the resistive element. The applied first bias voltage initiates a write operation at the memory cell. The word line signal is deasserted after a variable time duration based on a detection, during the write operation, of a current through the resistive element.

Abstract translation: 耦合到存储器单元的电阻元件的位线被设置为第一电压电平。 存储器单元可以是MRAM单元或RRAM单元。 电阻元件被配置为在存储单元的第一状态下具有第一电阻，并且在存储单元的第二状态下具有第二电阻。 通过存取晶体管选择性地耦合到存储单元的源极线被设置为第二电压电平。 字线信号被断言以在电阻元件上施加第一偏置电压。 所施加的第一偏置电压在存储器单元处启动写入操作。 基于在写入操作期间通过电阻元件的电流的检测，字线信号在可变持续时间后被断言。