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    Double-Gate Carbon Nanotube Transistor and Fabrication Method
    1.
    发明申请
    Double-Gate Carbon Nanotube Transistor and Fabrication Method 有权

    公开(公告)号：US20220302389A1

    公开(公告)日：2022-09-22

    申请号：US17308635

    申请日：2021-05-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jin Cai ,  Sheng-Kai Su

    IPC: H01L51/00 ,  H01L51/05 ,  H01L51/44

    Abstract: A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.

    Forming 3D Transistors Using 2D Van Der WAALS Materials
    3.
    发明申请
    Forming 3D Transistors Using 2D Van Der WAALS Materials 有权

    公开(公告)号：US20220359736A1

    公开(公告)日：2022-11-10

    申请号：US17874377

    申请日：2022-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Kai Su ,  Jin Cai

    IPC: H01L29/66 ,  H01L29/786 ,  H01L29/24

    Abstract: A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.

    Semiconductor device and manufacturing method thereof
    4.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11380785B2

    公开(公告)日：2022-07-05

    申请号：US16656210

    申请日：2019-10-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Sheng-Kai Su

    IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L29/24

    Abstract: A semiconductor device includes a substrate, a gate structure, semimetallic source/drain structures, and source/drain contacts. The gate structure is over the substrate. The semimetallic source/drain structures are respectively on opposite sides of the gate structure, in which a band structure of each of the semimetallic source/drain structures has a valence band and a conduction band at different symmetry k-points. The source/drain contacts land on top surfaces of the semimetallic source/drain structures, respectively.

    Forming 3D Transistors Using 2D Van Der WAALS Materials
    5.
    发明公开
    Forming 3D Transistors Using 2D Van Der WAALS Materials 审中-公开

    公开(公告)号：US20240290871A1

    公开(公告)日：2024-08-29

    申请号：US18657927

    申请日：2024-05-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Kai Su ,  Jin Cai

    IPC: H01L29/66 ,  H01L29/24 ,  H01L29/786

    CPC classification number: H01L29/66969 ,  H01L29/24 ,  H01L29/78696

    Abstract: A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.

    Semiconductor device and manufacturing method thereof
    6.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US12068405B2

    公开(公告)日：2024-08-20

    申请号：US17852079

    申请日：2022-06-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Sheng-Kai Su

    IPC: H01L29/76 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/7606 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7851

    Abstract: A method includes forming a semiconductor fin protruding above a substrate; forming a first 2D material layer across the semiconductor fin; depositing a gate material layer over the first 2D material layer; etching the gate material layer and the first 2D material layer to form a gate structure and a patterned first 2D material layer under the gate structure; laterally growing a second 2D material layer from the patterned first 2D material layer to beyond the gate structure; after laterally growing the second 2D material layer, forming gate spacers respectively on opposite sidewalls of the gate structure; and after forming the gate spacers, forming a third 2D material layer on the second 2D material layer until a combination of the third 2D material layer and the second 2D material layer comprises at least three or more monolayers of PtSe2.

    Forming 3D transistors using 2D Van Der Waals materials
    7.
    发明授权
    Forming 3D transistors using 2D Van Der Waals materials 有权

    公开(公告)号：US12009411B2

    公开(公告)日：2024-06-11

    申请号：US17874377

    申请日：2022-07-27

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sheng-Kai Su ,  Jin Cai

    IPC: H01L29/66 ,  H01L29/24 ,  H01L29/786

    CPC classification number: H01L29/66969 ,  H01L29/24 ,  H01L29/78696

    Abstract: A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.

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