公开(公告)号：US12131901B2

公开(公告)日：2024-10-29

申请号：US16921232

申请日：2020-07-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiang-Bau Wang

IPC: H01L21/02 ,  H01L29/165 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/0223 ,  H01L29/66795 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7848

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first fin structure and a second fin structure formed over the substrate. In addition, the second fin structure is higher than the first fin structure. The semiconductor structure further includes an isolation structure formed around the second fin structure and covering a top surface of the first fin structure and a gate structure formed over the first fin structure and the second fin structure. In addition, the top surface of the first fin structure is not flat.

公开(公告)号：US12107149B2

公开(公告)日：2024-10-01

申请号：US18302474

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Jhe Sie ,  Chen-Huang Huang ,  Shao-Hua Hsu ,  Cheng-Chung Chang ,  Szu-Ping Lee ,  An Chyi Wei ,  Shiang-Bau Wang ,  Chia-Jen Chen

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/76832 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

公开(公告)号：US11996466B2

公开(公告)日：2024-05-28

申请号：US17739708

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Huang Huang ,  Ming-Jhe Sie ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Shu-Uei Jang ,  An Chyi Wei ,  Shiang-Bau Wang ,  Ryan Chia-Jen Chen

IPC: H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

公开(公告)号：US20230343853A1

公开(公告)日：2023-10-26

申请号：US18343555

申请日：2023-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

Abstract: In a gate replacement process, a dummy gate and adjacent structure, such as a source/drain region, are formed. The dummy gate is removed, at least in part, using a directional etch to remove some but not all of the dummy gate to form a trench. A portion of the dummy gate remains and protects the adjacent structure. A gate electrode can then be formed in the trench. A two step process can be employed, using an initial isotropic etch followed by the directional etch.

公开(公告)号：US11652155B2

公开(公告)日：2023-05-16

申请号：US17752680

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Jhe Sie ,  Chen-Huang Huang ,  Shao-Hua Hsu ,  Cheng-Chung Chang ,  Szu-Ping Lee ,  An Chyi Wei ,  Shiang-Bau Wang ,  Chia-Jen Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/768 ,  H01L27/092

CPC classification number: H01L29/66545 ,  H01L21/76832 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/6656 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a dummy gate stack over a substrate; forming a first spacer layer over the dummy gate stack; oxidizing a surface of the first spacer layer to form a sacrificial liner; forming one or more second spacer layers over the sacrificial liner; forming a third spacer layer over the one or more second spacer layers; forming an inter-layer dielectric (ILD) layer over the third spacer layer; etching at least a portion of the one or more second spacer layers to form an air gap, the air gap being interposed between the third spacer layer and the first spacer layer; and forming a refill layer to fill an upper portion of the air gap.

公开(公告)号：US20220059685A1

公开(公告)日：2022-02-24

申请号：US17453869

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Li-Wei Yin ,  Shao-Hua Hsu

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.

公开(公告)号：US10163624B2

公开(公告)日：2018-12-25

申请号：US15599225

申请日：2017-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shiang-Bau Wang

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/51 ,  H01L29/267 ,  H01L29/78 ,  H01L29/165

Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first fin structure and a second fin structure formed over the substrate. The semiconductor structure further includes an isolation structure formed around the second fin structure and covering the first fin structure and a gate structure formed over the first fin structure and the second fin structure. The semiconductor structure further includes the first fin structure has a first height and the second fin structure has a second height higher than the first height, and the gate structure and the first fin structure are separated by the isolation structure.

公开(公告)号：US09659766B2

公开(公告)日：2017-05-23

申请号：US14577547

申请日：2014-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Shiang-Bau Wang

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/51 ,  H01L29/267 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/0223 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: Methods for forming semiconductor structures are provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a first sidewall layer to cover the first fin structure and the second fin structure over the substrate. The method for manufacturing a semiconductor structure further includes forming a second sidewall layer over the first sidewall layer and etching a top portion of the first fin structure and the first sidewall layer and the second sidewall layer formed over the top portion of the first fin structure to expose a portion of the first fin structure. The method for manufacturing a semiconductor structure further includes oxidizing the exposed portion of the first fin structure to transform the exposed portion of the first fin structure into an oxide structure formed over the first fin structure.

公开(公告)号：US12237416B2

公开(公告)日：2025-02-25

申请号：US17453869

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang ,  Li-Wei Yin ,  Shao-Hua Hsu

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L29/66

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.

公开(公告)号：US12237397B2

公开(公告)日：2025-02-25

申请号：US18343555

申请日：2023-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shiang-Bau Wang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

Abstract: In a gate replacement process, a dummy gate and adjacent structure, such as a source/drain region, are formed. The dummy gate is removed, at least in part, using a directional etch to remove some but not all of the dummy gate to form a trench. A portion of the dummy gate remains and protects the adjacent structure. A gate electrode can then be formed in the trench. A two step process can be employed, using an initial isotropic etch followed by the directional etch.