公开(公告)号：US20240371704A1

公开(公告)日：2024-11-07

申请号：US18774643

申请日：2024-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chun Chen ,  Ya-Yi Tsai ,  I-Wei Yang ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku

IPC: H01L21/8238 ,  H01L27/092

Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

公开(公告)号：US12132050B2

公开(公告)日：2024-10-29

申请号：US18526062

申请日：2023-12-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ryan Chia-Jen Chen ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yu-Hsien Lin ,  Ming-Ching Chang ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Yi-Chun Chen

IPC: H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H01L27/0886 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7842 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/3212

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

公开(公告)号：US20240313091A1

公开(公告)日：2024-09-19

申请号：US18671151

申请日：2024-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ryan Chia-Jen Chen ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yi-Chun Chen ,  Yu-Hsien Lin ,  Ming-Ching Chang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/785 ,  H01L21/845 ,  H01L27/1211

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.

公开(公告)号：US12087639B2

公开(公告)日：2024-09-10

申请号：US17883898

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chieh-Ning Feng ,  Chun-Liang Lai ,  Yih-Ann Lin ,  Ryan Chia-Jen Chen

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823481 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/6681 ,  H01L29/7834 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes forming a first fin and a second fin protruding above a substrate; forming isolation regions on opposing sides of the first fin and the second fin; forming a metal gate over the first fin and over the second fin, the metal gate being surrounded by a first dielectric layer; and forming a recess in the metal gate between the first fin and the second fin, where the recess extends from an upper surface of the metal gate distal the substrate into the metal gate, where the recess has an upper portion distal the substrate and a lower portion between the upper portion and the substrate, where the upper portion has a first width, and the lower portion has a second width larger than the first width, the first width and the second width measured along a longitudinal direction of the metal gate.

公开(公告)号：US11996466B2

公开(公告)日：2024-05-28

申请号：US17739708

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Huang Huang ,  Ming-Jhe Sie ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Shu-Uei Jang ,  An Chyi Wei ,  Shiang-Bau Wang ,  Ryan Chia-Jen Chen

IPC: H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

公开(公告)号：US20230260843A1

公开(公告)日：2023-08-17

申请号：US18306855

申请日：2023-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Chia Tai Lin ,  Chao-Cheng Chen

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/823431 ,  H01L29/6681 ,  H01L27/0886 ,  H01L21/76232 ,  H01L21/3081 ,  H01L21/823481

Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

公开(公告)号：US11670552B2

公开(公告)日：2023-06-06

申请号：US17239965

申请日：2021-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Chia Tai Lin ,  Chao-Cheng Chen

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/308 ,  H01L21/336

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/6681

Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

公开(公告)号：US11527443B2

公开(公告)日：2022-12-13

申请号：US17195189

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Yi-Hsuan Hsiao ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L21/8234 ,  H01L27/088

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

公开(公告)号：US20220384616A1

公开(公告)日：2022-12-01

申请号：US17818600

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Uei Jang ,  Ya-Yi Tsai ,  Ryan Chia-Jen Chen ,  An Chyi Wei ,  Shu-Yuan Ku

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/762

Abstract: A method of forming a semiconductor device includes etching a gate stack to form a trench extending into the gate stack, forming a dielectric layer on a sidewall of the gate stack, with the sidewall exposed to the trench, and etching the dielectric layer to remove a first portion of the dielectric layer at a bottom of the trench. A second portion of the dielectric layer on the sidewall of the gate stack remains after the dielectric layer is etched. After the first portion of the dielectric layer is removed, the second portion of the dielectric layer is removed to reveal the sidewall of the gate stack. The trench is filled with a dielectric region, which contacts the sidewall of the gate stack.

公开(公告)号：US20220384269A1

公开(公告)日：2022-12-01

申请号：US17818405

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ryan Chia-Jen Chen ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yu-Hsien Lin ,  Ming-Ching Chang ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Yi-Chun Chen

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.