公开(公告)号：US12265322B2

公开(公告)日：2025-04-01

申请号：US18365757

申请日：2023-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Hsun Lin ,  Pei-Cheng Hsu ,  Ching-Fang Yu ,  Ta-Cheng Lien ,  Chia-Jen Chen ,  Hsin-Chang Lee

IPC: G03F1/24

Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.

公开(公告)号：US11444080B2

公开(公告)日：2022-09-13

申请号：US17085121

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Yi-Hsuan Hsiao ,  I-Wei Yang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

公开(公告)号：US11294292B2

公开(公告)日：2022-04-05

申请号：US17085206

申请日：2020-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Yang Lin ,  Da-Wei Yu ,  Li-Hsin Wang ,  Kuan-Wen Lin ,  Chia-Jen Chen ,  Hsin-Chang Lee

IPC: G03F7/20 ,  G03F1/82 ,  G03F1/22

Abstract: An photolithographic apparatus includes a particle removing cassette selectively extendable from the processing apparatus. The particle removing cassette includes a wind blade slit and an exhausting slit. The wind blade slit is configured to direct pressurized cleaning material to a surface of the mask to remove the debris particles from the surface of the mask. The exhausting slit collects the debris particles separated from the surface of the mask and contaminants through the exhaust line. In some embodiments, the wind blade slit includes an array of wind blade nozzles spaced apart within the wind blade slit. In some embodiments, the exhausting slit includes array of exhaust lines spaced apart within the exhausting slit.

公开(公告)号：US11137684B2

公开(公告)日：2021-10-05

申请号：US16719118

申请日：2019-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Chih-Cheng Lin ,  Anthony Yen ,  Chin-Hsiang Lin

IPC: G03F7/20 ,  G03F1/50 ,  G03F1/24 ,  G03F1/26 ,  G03F1/42 ,  G03F1/48 ,  G03F1/54

Abstract: A method of performing a lithography process includes receiving a lithography mask and performing overlay measurement. The lithography mask includes a substrate that contains a low thermal expansion material (LTEM); a reflective structure over a first side of the substrate; an absorber layer over the reflective structure and containing one or more first overlay marks; and a conductive layer over a second side of the substrate and containing one or more second overlay marks. The second side is opposite the first side. The overlay measurement includes using the one or more first overlay marks in an extreme ultraviolet (EUV) lithography process or using the one or more second overlay marks in a non-EUV lithography process.

公开(公告)号：US10996553B2

公开(公告)日：2021-05-04

申请号：US16128863

申请日：2018-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Chang Hsueh ,  Huan-Ling Lee ,  Chia-Jen Chen ,  Hsin-Chang Lee

IPC: G03F1/22 ,  G03F1/24 ,  G03F1/58 ,  G03F1/48 ,  G03F1/52 ,  H01L21/027

Abstract: A reticle and a method for manufacturing the same are provided. The reticle includes a mask substrate, a reflective multilayer (ML), a capping layer and an absorption composite structure. The reflective ML is positioned over a front-side surface of the mask substrate. The capping layer is positioned over the reflective ML. The absorption composite structure is positioned over the capping layer. The absorption composite structure includes a first absorption layer, a second absorption layer, a third absorption layer and an etch stop layer. The first absorption layer is positioned over the capping layer. The second absorption layer is positioned over the first absorption layer. The third absorption layer is positioned over the second absorption layer. The etch stop layer is positioned between the first absorption layer and the second absorption layer. The first absorption layer and the second absorption layer are made of the same material.

公开(公告)号：US20210050350A1

公开(公告)日：2021-02-18

申请号：US17085121

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Hung ,  Chia-Jen Chen ,  Ming-Ching Chang ,  Shu-Yuan Ku ,  Yi-Hsuan Hsiao ,  I-Wei Yang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/283 ,  H01L29/78

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

公开(公告)号：US10816892B2

公开(公告)日：2020-10-27

申请号：US15966862

申请日：2018-04-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chien-Cheng Chen ,  Chia-Jen Chen ,  Hsin-Chang Lee ,  Shih-Ming Chang ,  Tran-Hui Shen ,  Yen-CHeng Ho ,  Chen-Shao Hsu

IPC: G03F1/36 ,  G03F1/76 ,  G03F1/78 ,  H01J37/317 ,  G03F7/20

Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.

公开(公告)号：US09360749B2

公开(公告)日：2016-06-07

申请号：US14260651

申请日：2014-04-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Yun-Yue Lin ,  Chia-Jen Chen ,  Hsin-Chang Lee ,  Anthony Yen

IPC: G03F1/62 ,  G03F1/64 ,  G03F1/00

CPC classification number: G03F1/62 ,  G03F1/142 ,  G03F1/64

Abstract: A pellicle structure, a pellicle-mask structure, and a method for forming the pellicle structure are provided. The pellicle structure includes a pellicle film made of a carbon-based material. In addition, the pellicle film is configured to protect a mask structure in a lithography process. The pellicle-mask structure includes a mask substrate having a mask pattern formed over the mask substrate and the pellicle frame disposed on the mask substrate. The pellicle-mask structure further includes the pellicle film disposed on the pellicle frame.

Abstract translation: 提供防护薄膜组件，防护薄膜组件，以及防护薄膜组件的形成方法。 防护薄膜组件包括由碳基材料制成的防护薄膜。 此外，防护薄膜被配置为在光刻工艺中保护掩模结构。 防护薄膜组件包括具有形成在掩模基板上的掩模图案和设置在掩模基板上的防护膜框架的掩模基板。 防护薄膜组件还包括设置在防护薄膜组件框架上的防护薄膜。

公开(公告)号：US09341937B2

公开(公告)日：2016-05-17

申请号：US14261809

申请日：2014-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun-Yue Lin ,  Chia-Jen Chen ,  Hsin-Chang Lee ,  Anthony Yen

IPC: G03B27/54 ,  G03F1/00 ,  G03F1/22 ,  G03F1/46

CPC classification number: G03F1/22 ,  G03F1/46

Abstract: A lithography system for an extreme ultra violet (EUV) mask is provided. The lithography system includes a coupling module. The coupling module includes at least one mask contact element configured to touch a peripheral area of the EUV mask. The lithography system also includes an ammeter having an end electrically connected to the EUV mask through the at least one mask contact element and another end connected to a ground potential. The ammeter includes a sensor configured to measure a current conducting from the EUV mask to the ground potential and a compensation circuit configured to provide a compensation current that is opposite to the current measured by the sensor.

Abstract translation: 提供了用于极紫外（EUV）掩模的光刻系统。 光刻系统包括耦合模块。 耦合模块包括被配置为触摸EUV掩模的外围区域的至少一个掩模接触元件。 光刻系统还包括电流表，其具有通过至少一个掩模接触元件电连接到EUV掩模的端部，另一端连接到接地电位。 电流表包括传感器，其被配置为测量从EUV掩模传导到地电位的电流;以及补偿电路，其被配置为提供与由传感器测量的电流相反的补偿电流。

公开(公告)号：US20150309405A1

公开(公告)日：2015-10-29

申请号：US14259194

申请日：2014-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Tsung Shih ,  Benjamin Lee ,  Chia-Jen Chen ,  Shang-Chieh Chien ,  Shinn-Sheng Yu ,  Jeng-Horng Chen ,  Anthony Yen

IPC: G03F1/64 ,  B29C71/02 ,  G03F7/20

CPC classification number: G03F1/64 ,  B29C71/02 ,  B29C2071/022 ,  G03F1/62 ,  G03F7/2002

Abstract: The present disclosure relates to a method of forming an EUV pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate at a position parallel to a top surface of the substrate. A pellicle frame is attached to the top surface of the substrate. The substrate is cleaved along the cleaving plane to form a pellicle film comprising a thinned substrate coupled to the pellicle frame. Prior to cleaving the substrate, the substrate is operated upon to reduce structural damage to the top surface of substrate during formation of the cleaving plane and/or during cleaving the substrate. Reducing structural damage to the top surface of the substrate improves the durability of the thinned substrate and removes a need for a support structure for the pellicle film.

Abstract translation: 本发明涉及一种形成具有连接到没有支撑网的防护薄膜框架的防护薄膜组件的EUV防护薄膜组件的方法，以及相关联的装置。 在一些实施例中，该方法通过在平行于衬底顶表面的位置处在衬底内形成切割平面来进行。 防护薄膜组件框架附接到基板的顶表面。 基底沿着切割平面切割以形成防护薄膜，该薄膜包含连接到防护薄膜框架上的薄化基底。 在切割基板之前，操作基板以在形成切割平面期间和/或在分离基板期间减少对基板顶表面的结构损伤。 降低对基板顶表面的结构损伤提高了薄板基板的耐久性，并且消除了对防护薄膜的支撑结构的需要。