公开(公告)号：US20230214575A1

公开(公告)日：2023-07-06

申请号：US18183056

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin Chuang ,  Szu-ju Huang ,  Shih-Yao Lin ,  Shih Feng Hong ,  Yin-An Chen

IPC: G06F30/398 ,  G06F30/394 ,  G06N5/04 ,  G06N20/00 ,  G06F30/327 ,  G06F30/396 ,  G06F30/3315 ,  G06F119/12

CPC classification number: G06F30/398 ,  G06F30/327 ,  G06F30/394 ,  G06N5/04 ,  G06N20/00 ,  G06F30/396 ,  G06F30/3315 ,  G06F2119/12

Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.