公开(公告)号：US11816417B2

公开(公告)日：2023-11-14

申请号：US17181429

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin Chuang ,  Henry Lin ,  Szu-ju Huang ,  Yin-An Chen ,  Amos Hong

IPC: G06F30/39 ,  G06F30/398 ,  G06N20/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/327

CPC classification number: G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06N20/00

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

公开(公告)号：US12099793B2

公开(公告)日：2024-09-24

申请号：US18446745

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin Chuang ,  Henry Lin ,  Szu-ju Huang ,  Yin-An Chen ,  Amos Hong

IPC: G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06N20/00

CPC classification number: G06F30/398 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06N20/00

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.

公开(公告)号：US20230214575A1

公开(公告)日：2023-07-06

申请号：US18183056

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin Chuang ,  Szu-ju Huang ,  Shih-Yao Lin ,  Shih Feng Hong ,  Yin-An Chen

IPC: G06F30/398 ,  G06F30/394 ,  G06N5/04 ,  G06N20/00 ,  G06F30/327 ,  G06F30/396 ,  G06F30/3315 ,  G06F119/12

CPC classification number: G06F30/398 ,  G06F30/327 ,  G06F30/394 ,  G06N5/04 ,  G06N20/00 ,  G06F30/396 ,  G06F30/3315 ,  G06F2119/12

Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.

公开(公告)号：US12019971B2

公开(公告)日：2024-06-25

申请号：US18183056

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin Chuang ,  Szu-ju Huang ,  Shih-Yao Lin ,  Shih Feng Hung ,  Yin-An Chen

IPC: G06F30/398 ,  G06F30/327 ,  G06F30/3315 ,  G06F30/394 ,  G06F30/396 ,  G06N5/04 ,  G06N20/00 ,  G06F119/12

CPC classification number: G06F30/398 ,  G06F30/327 ,  G06F30/394 ,  G06N5/04 ,  G06N20/00 ,  G06F30/3315 ,  G06F30/396 ,  G06F2119/12

Abstract: A violation prediction system includes machine learning circuitry trained based on past data to predict the presence of violations in electronic device designs after routing has been performed. The machine learning circuitry configured to predict, based on the past data and a pre-routing layout of an electronic device design, whether one or more violations would be present in in the electronic device design due to routing of the layout.

公开(公告)号：US20210174000A1

公开(公告)日：2021-06-10

申请号：US17181429

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin Chuang ,  Henry Lin ,  Szu-ju Huang ,  Yin-An Chen ,  Amos Hong

IPC: G06F30/398 ,  G06N20/00 ,  G06F30/392 ,  G06F30/394 ,  G06F30/327

Abstract: Systems and methods are provided for predicting systematic design rule check (DRC) violations in a placement layout before routing is performed on the placement layout. A systematic DRC violation prediction system includes DRC violation prediction circuitry. The DRC violation prediction circuitry receives placement data associated with a placement layout. The DRC violation prediction circuitry inspects the placement data associated with the placement layout, and the placement data may include data associated with a plurality of regions of the placement layout, which may be inspected on a region-by-region basis. The DRC violation prediction circuitry predicts whether one or more systematic DRC violations would be present in the placement layout due to a subsequent routing of the placement layout.