公开(公告)号：US12237227B2

公开(公告)日：2025-02-25

申请号：US17654408

申请日：2022-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan

IPC: H01L21/8234 ,  H01L27/105 ,  H01L29/78 ,  H01L49/02

Abstract: A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

公开(公告)号：US20240379659A1

公开(公告)日：2024-11-14

申请号：US18781059

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan

IPC: H01L27/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes: forming a fin protruding from a substrate; implanting an n-type dopant in the fin to form an n-type channel region; implanting a p-type dopant in the fin to form a p-type channel region adjacent the n-type channel region; forming a first gate structure over the n-type channel region and a second gate structure over the p-type channel region; forming a first epitaxial region in the fin adjacent a first side of the first gate structure; forming a second epitaxial region in the fin adjacent a second side of the first gate structure and adjacent a first side of the second gate structure; and forming a third epitaxial region in the fin adjacent a second side of the second gate structure.

公开(公告)号：US20230317714A1

公开(公告)日：2023-10-05

申请号：US17656935

申请日：2022-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/7851 ,  H01L21/26513 ,  H01L29/66795 ,  H01L29/66545

Abstract: A method includes: forming a fin protruding from a substrate; implanting an n-type dopant in the fin to form an n-type channel region; implanting a p-type dopant in the fin to form a p-type channel region adjacent the n-type channel region; forming a first gate structure over the n-type channel region and a second gate structure over the p-type channel region; forming a first epitaxial region in the fin adjacent a first side of the first gate structure; forming a second epitaxial region in the fin adjacent a second side of the first gate structure and adjacent a first side of the second gate structure; and forming a third epitaxial region in the fin adjacent a second side of the second gate structure.

公开(公告)号：US20250159969A1

公开(公告)日：2025-05-15

申请号：US19019957

申请日：2025-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan

IPC: H10D84/03 ,  H10D1/47 ,  H10D30/62 ,  H10D84/01 ,  H10D84/80

Abstract: A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

公开(公告)号：US20230420452A1

公开(公告)日：2023-12-28

申请号：US17848605

申请日：2022-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan ,  Wan-Lin Tsai ,  Chung-Liang Cheng

IPC: H01L27/06 ,  H01L29/8605 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L29/8605 ,  H01L29/7851 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66166

Abstract: Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET/embedded resistor combination may be utilized together in a common drain/common source contact design.

公开(公告)号：US20230290688A1

公开(公告)日：2023-09-14

申请号：US17654408

申请日：2022-03-11

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan

IPC: H01L21/8234 ,  H01L27/105 ,  H01L29/78 ,  H01L49/02

CPC classification number: H01L21/823431 ,  H01L27/105 ,  H01L29/7851 ,  H01L28/20 ,  H01L21/823437

Abstract: A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.