公开(公告)号：US20240375146A1

公开(公告)日：2024-11-14

申请号：US18782959

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yan-Jie Liao ,  Shih-Fen Huang ,  Chi-Yuan Shih

IPC: B06B1/02

Abstract: A method of forming a transducer includes depositing a first dielectric layer on a first electrode, patterning the first dielectric layer to form a plurality of first protrusions in a first region and a plurality of second protrusions in a second region, where a density of the plurality of first protrusions in the first region is different from a density of the plurality of second protrusions in the second region, and bonding the first dielectric layer to a second electrode using a second dielectric layer, where sidewalls of the second dielectric layer define a cavity disposed between the first electrode and the second electrode, and where the plurality of first protrusions and the plurality of second protrusions are disposed in the cavity.

公开(公告)号：US20230290688A1

公开(公告)日：2023-09-14

申请号：US17654408

申请日：2022-03-11

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan

IPC: H01L21/8234 ,  H01L27/105 ,  H01L29/78 ,  H01L49/02

CPC classification number: H01L21/823431 ,  H01L27/105 ,  H01L29/7851 ,  H01L28/20 ,  H01L21/823437

Abstract: A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

公开(公告)号：US11107630B2

公开(公告)日：2021-08-31

申请号：US16417797

申请日：2019-05-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Anderson Lin ,  Chun-Ren Cheng ,  Chi-Yuan Shih ,  Shih-Fen Huang ,  Yi-Chuan Teng ,  Yi Heng Tsai ,  You-Ru Lin ,  Yen-Wen Chen ,  Fu-Chun Huang ,  Fan Hu ,  Ching-Hui Lin ,  Yan-Jie Liao

IPC: H01G4/012 ,  H01G4/228 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/311 ,  H01G4/12 ,  H01L41/113 ,  H01L41/083 ,  H01L41/047

Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.

公开(公告)号：US20210202761A1

公开(公告)日：2021-07-01

申请号：US16728452

申请日：2019-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Li Cheng ,  Jyun-Ying Lin ,  Alexander Kalnitsky ,  Shih-Fen Huang ,  Shu-Hui Su ,  Ting-Chen Hsu ,  Tuo-Hsin Chien ,  Felix Ying-Kit Tsui ,  Shi-Min Wu ,  Yu-Chi Chang

IPC: H01L29/94 ,  H01L49/02 ,  H01L23/00 ,  H01L21/764 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/66

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a pillar structure abutting a trench capacitor. A substrate has sidewalls that define a trench. The trench extends into a front-side surface of the substrate. The trench capacitor includes a plurality of capacitor electrode layers and a plurality of capacitor dielectric layers that respectively line the trench and define a cavity within the substrate. The pillar structure is disposed within the substrate. The pillar structure has a first width and a second width less than the first width. The first width is aligned with the front-side surface of the substrate and the second width is aligned with a first point disposed beneath the front-side surface.

公开(公告)号：US20200227528A1

公开(公告)日：2020-07-16

申请号：US16837401

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US20180172627A1

公开(公告)日：2018-06-21

申请号：US15386545

申请日：2016-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsien Chang ,  Chun-Ren Cheng ,  Shih-Fen Huang ,  Ching-Hui Lin

IPC: G01N27/414 ,  H01L23/482

CPC classification number: G01N27/4145 ,  G01N27/4146 ,  H01L23/4825 ,  H01L29/786

Abstract: A semiconductor device including a biosensor with an on-chip reference electrode embedded within the semiconductor device, and associated manufacturing methods are provided. In some embodiments, a pair of source/drain regions is disposed within a device substrate and separated by a channel region. An isolation layer is disposed over the device substrate. A sensing well is disposed from an upper surface of the isolation layer overlying the channel region. A bio-sensing film is disposed along the upper surface of the isolation layer and extended along sidewall and lower surfaces of the sensing well. A reference electrode is disposed vertically between the bio-sensing film and the isolation layer.

公开(公告)号：US09236326B2

公开(公告)日：2016-01-12

申请号：US14262582

申请日：2014-04-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Alexander Kalnitsky ,  Hsiao-Chin Tuan ,  Shih-Fen Huang ,  Hsin-Li Cheng ,  Felix Ying-Kit Tsui

IPC: H01L21/311 ,  H01L23/48 ,  H01L21/768 ,  H01L21/265 ,  H01L21/22

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.

Abstract translation: 提供半导体结构及其制造方法。 半导体结构包括具有顶表面和底表面的晶片衬底，以及通过晶片衬底的顶表面和底表面由深沟槽绝缘体限定的晶片衬底中的导电柱。 制造半导体结构的方法包括以下步骤。 从晶片衬底的顶表面形成深沟槽以在晶片衬底中限定导电区域。 导电区域掺杂有掺杂剂。 深沟槽填充有绝缘材料以形成深沟槽绝缘体。 并且晶片衬底从晶片衬底的底表面变薄以暴露深沟槽绝缘体并隔离导电区域以形成导电柱。

公开(公告)号：US12237227B2

公开(公告)日：2025-02-25

申请号：US17654408

申请日：2022-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan

IPC: H01L21/8234 ,  H01L27/105 ,  H01L29/78 ,  H01L49/02

Abstract: A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.

公开(公告)号：US20240379659A1

公开(公告)日：2024-11-14

申请号：US18781059

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan

IPC: H01L27/06 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

Abstract: A method includes: forming a fin protruding from a substrate; implanting an n-type dopant in the fin to form an n-type channel region; implanting a p-type dopant in the fin to form a p-type channel region adjacent the n-type channel region; forming a first gate structure over the n-type channel region and a second gate structure over the p-type channel region; forming a first epitaxial region in the fin adjacent a first side of the first gate structure; forming a second epitaxial region in the fin adjacent a second side of the first gate structure and adjacent a first side of the second gate structure; and forming a third epitaxial region in the fin adjacent a second side of the second gate structure.

公开(公告)号：US20230317714A1

公开(公告)日：2023-10-05

申请号：US17656935

申请日：2022-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Qiang Wen ,  Shih-Fen Huang ,  Shih-Chun Fu ,  Chi-Yuan Shih ,  Feng Yuan

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/7851 ,  H01L21/26513 ,  H01L29/66795 ,  H01L29/66545

Abstract: A method includes: forming a fin protruding from a substrate; implanting an n-type dopant in the fin to form an n-type channel region; implanting a p-type dopant in the fin to form a p-type channel region adjacent the n-type channel region; forming a first gate structure over the n-type channel region and a second gate structure over the p-type channel region; forming a first epitaxial region in the fin adjacent a first side of the first gate structure; forming a second epitaxial region in the fin adjacent a second side of the first gate structure and adjacent a first side of the second gate structure; and forming a third epitaxial region in the fin adjacent a second side of the second gate structure.